Status Register

Introduction to ARM Assembly Language

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ALU’s produce several output signals to provide information about the results, or status, of the most recently completed instruction. These output signals always include the four basic signals, most typically named N, Z, C, and V, and they always have the same definitions:

  • N is a ‘1’ if the last ALU operation produced a negative number;
  • Z is a ‘1’ if the last operation produced a ‘0’ result;
  • C is a ‘1’ if the last operation produced a carry-out;
  • V is a ‘1’ if the last operation produced an overflow condition.

These signals are inputs to the controller state machine, where they are used to “conditionally control” the execution of certain instructions. They are often called condition codes or status bits, and the two terms are equivalent.

We have already seen that almost all ARM instructions can include a check of the condition codes, and that execution can be made dependent on certain conditions. For example, the instruction LDRMI R0, [R1] would load R0 with data at a memory location pointed to by R1, but only if the last executed instruction produced a negative number. As a further example, the instruction BEQ loop would branch to an instruction with the label “loop”, but only if the last instruction produced a ‘0’ result.

Certain instructions exist only to update the status bits (that is, they do not change any register contents). Compare instructions subtract the second operand from the first, update the status bits, and discard the result. CMP R1, R0 will subtract R0 from R1, and update the status bits without changing any register contents. If C = ‘1’ and Z = ‘0’, then R1 is greater than R0; if both are ‘1, they are equal, and if both are ‘0’ R1 is less than R0. Test instructions behave similarly.

Status bits are collected into the “Current Program Status Register” as shown below. The CPSR also contains other status information that is useful to the operating system, more so than to user programs. When an user-application reads the status register, it actually reads a copy of the CPSR called the “Application Program Status Register” or APSR. There aren’t actually two registers – the APSR is the “read only” version of the CPSR, with certain bits hidden from view. The ASPR is also shown below.

Figure 1. ARM APSR and CPSR Registers
Figure 1. ARM APSR and CPSR Registers

The nine status bits are outputs from ALU, and they are sampled and stored in the status register. They show the results of the most recent ALU operation:

  • N: Negative flag – set to 1 if ALU result is negative
  • Z: Zero flag – set to 1 if ALU result is zero
  • C: Carry flag – set to 1 on carry-out of ALU bit 31
  • V: Overflow condition flag – set to 1 on overflow
  • Q: Saturation flag – set to 1 on “saturation” of certain DSP-related instructions
  • GE: Greater than or equal flags, set for certain byte or half-word instructions

The other bits in the CPSR are defined in the ARM Architecture Reference Manual; we won’t access them in this course.