A Brief History of Verilog

The origins and intent of the Verilog language

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A brief history of Verilog

Hardware Description Languages (VHDL and Verilog) were introduced in the mid-1980s as “specification” languages, so that engineers could precisely and unambiguously describe the desired behaviors of a given circuit. At the time, very-large-scale-integrated (VLSI) circuits were becoming more common, and engineers working on large teams needed a way to accurately create and disseminate detailed specifications. It was becoming clear that maintaining an accurate “design to” specification, in a format that was understood by all designers, was imperative.

The VHDL (and Verilog) languages were written as specification languages, to give engineers a uniform way to precisely specify large and complex systems. Further, the HDL sources could be simulated, so that engineers could validate a system’s performance before the large, manual task of creating a physical circuit was started.

In the early days, HDL designs were given to large teams of technicians, and they would create physical circuits that met the HDL requirements. Automatically creating a real, physical circuit from an HDL source was not a part of the plan. But within a few years, engineers realized that creating a physical circuit based on an HDL description was a fairly low-level and repeatable task. By the early 1990’s, a new class of computer programs called “synthesizers” began appearing. Synthesizers take high-level, behavioral circuit descriptions, and produce a low-level, highly detailed structural descriptions. By the late 1990’s, the entire base of engineers, representing one of the largest economic engines on Earth, adopted their use. Such rapid change would not have happened if synthesizers didn’t offer overwhelming benefits.

But such rapid change also means that tools, methods, and technologies are still evolving; almost as soon as tools and technologies become widespread and well accepted, they are replaced by a new generation of more abstract and more powerful tools. CAD tool architects are constantly ushering in new design tools and methods, and so design engineers must constantly learn how to use newer and more powerful tools – a trend that will continue for some time.

Digital design CAD tools can be placed in two major categories: the “front-end” tools used to capture and simulate a design, and “back-end” tools that synthesize, analyze and implement a design in some target technology. Front-end tools work largely with virtual circuits, and back-end tools work with physical circuits. Several companies produce CAD tool environments, with some focusing on front-end tools, some on back-end tools, and some on both. For the most part, they are relatively similar, and engineers can move between tools without too much difficulty. Two major front-end HDLs have emerged (Verilog and VHDL), and they are both text-based and highly portable between design environments. Both are similar in appearance and application, and both have their (slight) relative strengths and advantages. Verilog is more common, and is used in about 80% of industrial designs. It should be noted that after learning one of the two languages, the other can be adopted quickly.

HDLs have allowed design engineers to drastically increase their productivity - a single engineer today is as productive as a small team of engineers just a few years ago. Further, a wide range of engineers can use HDLs to specify complex circuits, instead of just a relative few with highly specialized training and experience. The widespread use of these more powerful and abstract tools has changed the role of the design engineers. Instead of teams of engineers creating robust structural circuits based on designs and architectures produced by a few “system architects”, individual engineers must be able to craft system-level behavioral circuit definitions that provably meet design requirements, and they must understand synthesis and other CAD tool processes so that results can be critically examined and interpreted. Relieving engineers of the work of creating structural circuits doesn’t always mean less work, but it does change the focus. Now, engineers must be able to critically examine, verify and validate post-synthesis designs, to make sure they meet the original design intent and specification.

Verilog HDL was invented by Phil Moorby and Prabhu Goel around 1984. It was developed as a proprietary hardware modeling language, owned by Gateway Design Automation Inc. At that time, the language was not standardized, and it was extensively modified between 1984 and 1990.

In 1990, Gateway Design Automation Inc was acquired by Cadence Design System, which is now one of the biggest suppliers of electronic design technologies and engineering services in the electronic design automation (EDA) industry. Cadence recognized the value of Verilog, and realized that if Verilog remained as a closed language, the pressure of standardization would eventually drive people to shift to VHDL. So in 1991 the Open Verilog International (OVI) initiative was organized by Cadence, and Verilog was transferred to public domain under the name of OVI. It was later submitted to IEEE and became IEEE standard 1364-1995, commonly referred as Verilog-95. In 2001 and again in 2005, various extensions and modifications to Verilog were adopted, resulting in the IEEE standard 1364-2005, or Verilog-2005. Also in 2005, “System Verilog”, a superset of Verilog-2005 with many new features and capabilities to aid design verification, was published. As of 2009, System Verilog and the Verilog language standards were merged into System Verilog 2009 (IEEE Standard 1800-2009), which is now one of the most popular languages for IC design and verification. The Xilinx® Vivado Design Suite, released in 2013, can support Verilog 2005 and System Verilog for FPGA design and verification.