Global Timer Module

Configuring the Global Timer on ZYNQ


Global Timer

The global timer (GTC) is a part of the ARM A9 core. It is a 64 bit timer, which increments at the peripheral clock rate. In the case of the blackboard, that means 333.333MHz, approximately 3ns per tick. Being 64-bits long, the counter goes from zero to 18,446,744,073,709,551,615. The time it takes to overflow (rollover back to zero) is approximately 55.34 million seconds (3ns * 2^64) which is around 1754.8 years. The timer includes a comparator, which can generate an interrupt. Timer interrupts are particularly useful, as the processor doesn’t need to poll the timer and can be interrupted when needed. Timers interrupts are a good way to implement periodically occuring events.

Using the Global timer

The global timer has 5 registers, 2 of which are 64-bit (each half of the register must be accessed seperatly). They are listed below

Global Timer Counter: 64-bit register holding the current global timer value.

Global Timer Control: Configures the operation of the timer.

Global Timer Interrupt Status: holds a single flag for interrupt status.

Global Timer Comparator Value: 64-bit register holding Comparator value.

Auto-increment Register: 32-bit register holds value for incrementing comparator value at match events.


Register Address
Count Low (lower 32 bits of counter) 0xF8F00210
Count High (upper 32 bits of counter) 0xF8F00214
Control Register 0xF8F00208
Interrupt Status Register 0xF8F0020C
Comparator Low 0xF8F00210
Comparator High 0xF8F00214
Auto Increment Value 0xF8F00218

GTC Control register

The fields of the GTC’s control register are shown and detailed below

Global Timer Control Register
Global Timer Control Register

Timer enabled[0] This bit enables the timer’s operation

Comp enable[1] setting this bit enables comparison events to occur.

IRQ enable[2] setting this bit enables interrupts to be generated from the global timer. Interrupts will occur whenever a comparison event happens.

Auto-increment[3] when this bit is set, a comparison event will automatically increment the value in the Comparator Value register by the value in the Auto-increment register. This enables the timer to generate events at regular intervals.

Prescaler[15:8] 8-bit field that determines the divisor for the clock. The clock is divided by 2^n where n is the value of the scaler. When enabled, the count register will increment at the peripheral clock divided by 2^n (The blackboard’s peripheral clock is at 333.333MHz).

All other bits are reserved and must be cleared.

Interrupt status register

The Interrupt status register holds a single bit in it’s lowest bitfield. This bit is set when the IRQ enable and Comp enable bits are set in the control register. This flag can be cleared by writing a 1 to the register.

Timer Counter and Comparator Registers

The timer has 2 64-bit registers. The Timer Counter register holds the current value of the timer. It can be read at any time, but before wrting a new value to these registers, the timer should be disabled.

The Comparator Value register holds the current comparator value. It can be written at any time.

Both of these registers are 64-bit wide and must be accessed in 32-bit segments.

Timer interrupts

The global timer generates interrupts when the IRQ-en bit is set, the COMP-enable bit is set, and a comparison event occurs (The counter increments to a value that matches the comparator value). The interrupt behavior can be defined by the auto-increment function.

When auto-increment is disabled, the timer is in ‘one-shot’ mode; It will count up to the comparator value then generate a single interrupt. The timer will continue to increment past the comparator value and not trigger another interrupt until the counter rolls over and reaches the comparator value again.

When auto-increment is enabled, the timer will generate periodic interrupts. It will count up to the comparator’s value and generate an interrupt. When auto-increment is enabled and the values in the counter and comparator match, the comparator’s value will be incremented by the value found in the auto-increment register. The timer will continue counting and when it reaches this new value it will generate an increment and again add to the comparator value. This will continue until disabled. Thus, with auto increment enabled, the rate of interrupts can be defined by setting the value of the auto-increment register along with the prescaler value.

Configuring the Global Timer for interrupts

Steps are given below for configuring interrupts for the

To Configure the global timer for a single interrupt (one-shot mode):

  1. Disable the timer and interrupts by clearing the bits in the control register.
  2. Load the desired comparator value into the lower and higher comparator registers.
  3. Reset the counter to zero by writing to the low and high count registers.
  4. Configure the timer to run in one-shot mode, by clearing the auto-inc bit in the control register.
  5. Enable the timer and interrupts by setting the en, IRQ, and Comp bits in the control register.

To configure the global tiemr for periodic interrupts:

  1. Disable the timer and interrupts by clearing the bits in the control regsiter.
  2. Load the comparator with the counter value for the first interrupt to occur at
  3. Load the auto-increment register with the value desired for time between interrupts
  4. Configure the timer to automatically increment by setting the auto-inc bit in the control register.
  5. Enable the timer and interrupts by setting the en, IRQ, and Comp bits in the control register.

The GTC is interrupt ID #27 in the GIC. The GIC must be configured before it can forward interrupts from the global timer to the processor. The steps to configure the GIC for the GTC are the same as any other interrupt source. The GTC’s interrupt sensitivity and polarity fields in the GIC must be set to positive-edge sensitive.

Servicing interrupts

The timer’s interrupt bit, in the interrupt status register, will be set when the comp and IRQ bits are set in the control register and when the comparator and count value match. The interrupt status flag is ‘sticky’ meaning it must be cleared manually. Be sure to clear the bit in the interrupt service routine,