Switch Bounce

The mechanics of switch bounce, and what to do about it

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When a mechanical switch opens or closes (for example, when user depresses a pushbutton), it is very typical that the mechanical apparatus used to “close” or “make” the circuit bounces for a short time. That is, contact is made initially between the switch contacts, but then due to mechanical elasticity, imperfections in manufacturing, and other factors, contact is then broken for short period, then remade, then broken again, etc., for some amount of time. This “switch bounce” phenomenon is typically very short lived, with each make-break cycle happening over a few microseconds, and with perhaps one to several such cycles per switch actuation. Smaller switches might exhibit bounce activity for 10-100us, while large switches might bounce for upwards of 1ms.

Figure 1. Typical switch bounce behavior for a 0-1 transition
Figure 1. Typical switch bounce behavior for a 0-1 transition

If a switch output is over-sampled at too high of a frequency (i.e., with a period that is less than the bounce time), multiple switch closures and openings can be erroneously detected for a single activation. In figure 2 below, the sample rate is much less than the bounce time, and so multiple transitions are detected on adjacent clock edges.

Figure 2. Over-sampled switch output
Figure 2. Over-sampled switch output

If a switch output is sampled at too low a frequency, unacceptable latency (or response time) can be introduced, and a rapid switch activation-deactivation could possibly be missed. To avoid these issues, switches outputs should be sampled at a period that approximates the bounce time, and additionally, a simple filter should also be applied to the samples. In the figure below, the sample period is longer, and close to the switch bounce time.

Figure 3. Well-sampled switch output
Figure 3. Well-sampled switch output

Sample period

The switch sample period should approximate the bounce time. For example, if a switch is known to exhibit 100us of bounce, then a sample clock with a 100us period (or 10KHz) would be a good choice – only one sample per bounce period is possible, eliminating the possibility of reacting multiple times to a single activation.

Switch manufacturers typically have documentation that provides data on bounce performance, but it can be hard to find. A very conservative bounce period estimate for smaller switches might be in the realm of 1ms – in all likelihood, small switch bounce periods are probably on the order of 10us. If a system can tolerate latency, the longer the sample period, the better.

Simple filter

Even with an appropriate sample clock, there is still risk of sampling a “bounce” that is not indicative of the final switch state. A good and simple remedy is to sample the switch output twice on consecutive sample clocks, and then to identify a switch transition only if the two consecutive samples match. For example, if a switch output is normally low, then a 0-1 transition would only be recognized after two consecutive ‘1’ samples. Likewise, a 1-0 transition would only be recognized after two consecutive ‘0’ samples. This simple filter strategy only works if the sample clock period approximates the bounce period.

An input “debouncing” state machine

A simple four-state machine can be designed to implement the debounce filter. Assuming the input signal is normally low, then in the first state, the “raw” input signal (directly from the switch) is sampled using the slow clock that approximates the bounce period. The machine holds in this state until the input is sampled high, and then transitions to a new state. In this second state, the input is again sampled – if the input is low, then a bounce was detected and the machine returns to the first state. But if the input is high, then a second consecutive was detected, and the machine can branch to a third state and output the “clean” signal. Now, the process repeats, but waiting on two consecutive 0’s. (Note: a state machine sketch would have made this discussion easier – but that’s your job!)

Figure 4. Block diagram for an input debouncing state machine circuit
Figure 4. Block diagram for an input debouncing state machine circuit