Analog and Digital Displays

Background

5034

Background

When computers became widespread in the 1980’s, cathode ray tubes (CRTs) were the only viable display devices. Manufacturers needed to produce displays that could be used with any given computer, and that drove the need for industry-wide specifications. The VESA organization was formed in 1987 to produce such specifications, and VESA quickly grew into the dominant (and only) specification body. VESA produced “analog” specifications for higher resolution CRTs until 2006, and then switched to their “digital” Display Port specification. About that same time (2003), the HMDI organization formed and promoted their own digital display specification. Both digital specifications grew from the analog specifications that targeted CRT displays, so some background information on analog/CRT displays is useful.

Analog Displays and Controllers

Early computer displays used CRTs. CRTs use amplitude-modulated moving electron beams (or cathode rays) to display information on a phosphor-coated screen. Three identical electron beams (one for red, one for blue, and one for green) are shot from finely-pointed cathodes (called electron guns) at one end of the tube, and they accelerate towards the phosphor-coated and electrically charged display surface at the other end. The beams impact and excite the colored phosphor that coats the inner side of the display surface in just a few nanoseconds, and they leave a glowing presence for several hundred microseconds after the beam is removed.

A 20KV+ electrostatic field between the cathodes and the display surface (the anode) pulls electrons towards the display surface, and electromagnetic “deflection” circuits steer these electron beams (called cathode rays) as they travel through the tube. The deflection circuits work by driving a linearly increasing current through a fixed coil of wire wrapped around the cathode tube. The resulting electromagnet generates an increasing magnetic field, and that field forces the cathode ray to curve to an increasing degree. By controlling the deflection current, the cathode ray can be sent to any spot on the display.

Figure 1. CRT display.
Figure 1. CRT display.

One electromagnetic deflection circuit forces the electron beam to travel from side to side across the display surface at a relatively high frequency (about 30KHz) to produce display rows, and a second deflection circuit forces the beam to travel from the top to bottom of the display at about 60Hz to produce display frames. Working together, these two deflection circuits direct the beam through every pixel area on the display 60 times each second (this top-to-bottom, side-to-side screen-painting path of the beam is known as a raster pattern).

Current through the electron guns sets the intensity of the cathode ray, and the video signal sets the current through the electron gun. Therefore, the video signal sets the brightness of any given pixel. As the cathode ray traverses a given pixel location, the video signal amplitude at that exact time determines the brightness of that pixel. A video controller circuit must establish a stable, repeating current through the deflection circuits to create a stable display, and it must ensure the video signal is synchronized to the deflection circuits so the correct video signal amplitude is applied at the right time.

Information is only displayed when the beam is moving in one direction (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Typically, about 20% of the time spent scanning the display surface is needed to reset the beams (called beam retrace). During retrace, no information can be displayed, and so these retrace times are called “blanking” periods. The controller circuit must allow adequate time for information display and for retrace periods.

CRT deflection circuits were designed to support different sized raster patterns (that is, different numbers of rows and columns). A timing signal called Horizontal Sync (HS) sets the frequency for the CRT’s horizontal deflection circuit, and a second signal called Vertical Sync (VS) sets the vertical deflection frequency. Both signals are 3V-5V digital signals, with small pulses at the desired frequency. Those pulses tune the deflection circuits to an exact frequency, and they ensure its stability. A display controller circuits must produce these synchronizing pulses at the desired frequency, and it must also ensure that video data is applied to the electron guns at the correct time.

The display controller uses a pixel clock to set the time that each pixel is active. A horizontal counter counts some number of pixel clocks per row, and then generates a pulse at the end of each row to reset the horizontal deflection circuit. A second counter (the vertical counter) counts some number of rows per frame, and then generates a pulse to reset the vertical deflection circuit. Both counters must count out more pixels (or more rows) than are displayed, to allow for beam retrace time. Note that every pixel on the display will have a unique address formed by the contents of the horizontal and vertical counters; about 80% of the addresses will correspond to a displayable pixel, and about 20% to retrace.

Video data typically comes from one or more memory bytes assigned to each pixel location. The controller can use the address formed by the horizontal and vertical counters to index into video memory as the beams move across the display, and retrieve and apply video data at precisely the time the electron beam is moving across a given pixel.

Figure 2. VGA raster pattern and synchronization.
Figure 2. VGA raster pattern and synchronization.

Analog display systems use a blue 15-pin “D-sub” connector to transport the five required signals, including the Horizontal Sync (HS) and Vertical Sync (VS) timing signals that control the CRT deflection circuits, and the Red ( R), Green (G) and Blue (B) data signals that control pixel brightness. Data signals are analog signals that range from 0V-0.7V, and they are applied directly to the electron guns – the higher the voltage, the brighter the pixel.

Figure 3. VGA/Analog display connector pinout
Figure 3. VGA/Analog display connector pinout

All necessary timing and control signals can be produced using a set of comparators and two counters. In the figure below, PX and PY are the X and Y screen coordinates – they can be used to index into memory, or to create images in given screen areas.

Figure 4. VGA controller block diagram.
Figure 4. VGA controller block diagram.

Digital Displays and Controllers

Two main specifications exist for digital displays and controllers – Display Port, owned and maintained by VESA, and HDMI, owned and maintained by the HDMI organization. Both standards are in general use, both support very high resolution displays, and both use high-speed TMDS signaling (TMDS stands for Transition Minimized Differential Signals). TMDS signals can run into the GHz range needed for 4K and beyond displays.

HDMI controllers maintain the concept of a pixel clock and three color signals (R, G, B). The pixel clock defines each pixel time, but the color data is sent as a TMDS encoded digital word (and so the color data must run at a much higher frequency, since each pixel needs up to 8 bits per color). Like with analog displays, pixel data must be sent at precisely the right time in order to align with the correct pixel position.

Digital displays do not require any retrace – the pixel at the start of one row could immediately follow the pixel at the end of the preceding row. Nevertheless, HDMI controllers use far more pixel clocks per frame than there are displayable pixels. The extra clocks (about 15% of the total clocks per frame) are used to move audio and other control data. The same TMDS signals used to transport video data are repurposed to transport other data during the non-displayed pixel clocks.

While it is certainly possible to design a digital display controller, it is not trivial. Real Digital provides a VGA-to-HDMI IP block that allows a simpler analog/VGA controller to drive an HDMI monitor. Using this IP block, users can design a VGA-compatible controller that produces HS, VS, the R, G, and B color signals (and each color can be defined by 1 to 8 bits), and an additional Video Data Enable (VDE) signal (VDE is driven high when valid video data is present, and low during blanking periods).