The SPI Bus

Serial Peripheral Bus


The Serial Peripheral Interface bus (SPI) is a synchronous serial communication system used to transfer low- to medium-speed data (up to about 5MBytes/second) in embedded systems. The SPI bus has become one of the most popular serial busses used in embedded systems because it offers good data transfer rates, it is simple and inexpensive to implement, and it is supported by a large number of devices and software drivers. SPI busses are commonly used to communicate with a wide array of peripheral devices including memories, sensors of all kinds, analog-to-digital converters, real-time clocks, displays, and a variety of other devices.

SPI is a point-to-point bus that has a single master and one or more slaves. It uses four signals: slave select (SS), master out slave in, (MOSI), master in slave out (MISO), and clock (SCLK). The master and slave both contain shift registers, and the SPI bus connects them together to make one long, distributed shift register. In operation, data to be sent is loaded into the master shift register (for a write) or the slave shift register (for a read), and the SPI controller issues enough clocks to shift all data bits out of one shift register and into the other. Typically, the MSB is shifted out first.

Because the SPI bus creates one long shift register that is partly in the master and partly in the slave, data is rotated through both devices. To read data from an SPI device, you must shift data out of the slave and in to the master, and at the same time shift data out of the master and in to the slave - even if there is no useful data to send to the slave. In fact it is often the case that an SPI-connected device (like a sensor) produces, but does not consume data – in this case, MOSI data is irrelevant (a “don’t care”), and either 1’s or 0’s can be shifted. At any point, the master or slave can overwrite data in their local shift registers.

Figure 1. Simplified SPI block Diagram
Figure 1. Simplified SPI block Diagram

SPI devices are inherently full duplex, master-slave systems with a single master. The master device originates the frame for reading and writing. Multiple slave devices are supported through selection with individual slave select (SS) lines. A single slave system uses one SS signal. Any number of slaves can be present, and in the most typical multi-slave arrangement, each slave has its own select signal. It is possible to use a daisy-chain arrangement to make one long shift register.

Note that in the multi-slave, non-daisy-chain arrangement, the single MISO signal can be driven from multiple slave devices. This requires that the slave’s MISO signal use a three-state buffer enabled by SS. Most SPI devices do use three-state buffers on their MISO signals, but you should always check a devices data sheet to be sure.

Figure 2. SPI Bus Configurations
Figure 2. SPI Bus Configurations

Data frames

An SPI data frame is defined by the SS signal, and no start or stop bits are used (so, every SCLK transfers a data bit). The master must drive the SS signal to a given slave in order to initiate a read or a write. After SS is asserted (typically low), eight or more clock transitions can be asserted depending on the number of bits that must be transferred. Most SPI devices use units of 8-bit bytes, but any data size can be used.

Figure 3. Basic SPI framing
Figure 3. Basic SPI framing

In some devices, SS assertion not only initiates a data frame, but also enables the device to perform a function. For example, some analog to digital converters use a transition on SS to start a conversion, and then specify a waiting period (during which time the conversation takes place) before the first assertion of SCLK.

Clock polarity and phase

SPI clock speeds of 50MHz are common, and most SPI controllers can operate to at least 20MHz. For maximum flexibility, the SPI definition allows different clocking configurations. A “polarity 0” SCLK idles at 0, and the first rising edge after SS is asserted is the “leading edge” that defines the first clock pulse. A “polarity 1” SCLK idles at 1, and the first falling edge after SS is asserted is the “leading edge” that defines the first clock pulse.

Figure 4. Clock Polarity
Figure 4. Clock Polarity

The “clock phase” (CPHA) defines which clock edge is the active edge that is used to read data. For CPHA = 0, data is captured on the leading edge of the clock signal (rising for CPOL=0, and falling for CPOL=1), and for CPHA = 1, data is captured on the next edge (falling for CPOL=0, falling for CPOL=1).

The MOSI and/or MISO signals must be stable when they are read, so they must be driven before the active read clock edge. For CPHA = 1, data is read on the next clock edge following the leading edge, and not on the leading edge. So for CPHA = 1, data can be driven out on the first leading clock edge after SS is asserted. Data can be consumed on the next edge that is ½ clock period away from the leading edge, or if more time is needed, on the next active edge that is a full clock period away.

Figure 4. Clock Phase 1
Figure 4. Clock Phase 1

For CPHA = 0, data is read on the leading edge, so the data to be consumed must be driven on the last edge of the preceding data frame. Data can be shifted out on the same edge (the leading edge), or on the next edge ½ clock period away.

Figure 5. Clock Phase 0
Figure 5. Clock Phase 0

Using CPOL and CPHA as two bits in a binary number, four common SPI modes can be defined as shown. SPI mode 0 is commonly used, but you must check the data sheet of any SPI device you might use.

Advantages and Disadvantages of using the SPI bus

Digital systems designers often have several busses to choose from when connecting peripheral devices, including SPI, I2C, UART, CAN and others. Compared to the other busses, SPI offers several advantages and disadvantages.

SPI offers several advantages:

  • Since the transmitter and receiver both use the same clock, a precision clock is not needed – the clock period, phase and duty cycle can vary widely, provided the minimum clock period requirement is met;
  • No address needed since SPI is point-to-point;
  • Signals are unidirectional so three state buffers and bus turn-around circuits are not needed;
  • Any data size can be used (not just 8 bits);
  • No arbitration or clock extraction is needed since the clock is included in the bus;
  • No special transceivers are needed – SPI signals are simple logic-level signals.

SPI also has some relative disadvantages compared to other buses:

  • Since the bus in point-to-point, more pins are required to interface with more devices;
  • The SPI protocol does not include flow control, data acknowledge, or error checking, so the master has no good way to know whether data was accurately sent and received;
  • Only one master is defined, so the bus cannot be shared.

In may designs, the advantages outweigh the limitations, and SPI remains one of the most popular interconnect busses used in embedded systems.

QSPI and SD Cards

A superset of the SPI interface called “Quad SPI” or QSPI follows the same general bus timings and protocols, but adds three more data signals to quadruple the data rate. Most QSPI devices reset into regular SPI mode, and then are configured for QSPI operations. Rather than define three new signals, many QSPI devices overload existing pins by redefining them as additional data signals when operating in QSPI mode. An example pinout is shown below, but consult the data sheet for a particular part’s pin definitions.

Figure 6. QSPI pins
Figure 6. QSPI pins