I2C Bus

Overview of the I2C Bus

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The Inter-integrated circuit bus (IIC or I2C bus) is a synchronous, multi-master/multi-slave, packet switched serial data bus. It is widely used for low-speed communications in digital systems on board and off board.

I2C uses two bidirectional, open-drain signals called SDA (serial data) and SCL (serial clock). Both signals must be pulled to the high side of the power supply (typically 5V or 3.3V) by a low-valued resistor (2.2KOhm is typical). The signals are open-drain so that any node can be the master and drive the other nodes without damaging them (i.e., multi-master). The open-drain, multi-node physical transport limits I2C bus speeds; 100Kbits/second is the “standard mode” data rate and 400Kbits/sec is the “fast mode” data rate (although some of the latest implementations are up to 3.4MHz).

Figure 1. I2C is a multi-master, multi-slave bus
Figure 1. I2C is a multi-master, multi-slave bus

The I2C bus is synchronous, with the SCL signal defining when the SDA signal is transporting valid, stable data. Whatever the bit rate, the actual data rate is slower because the I2C protocol introduces some overhead. Addresses and “acknowledge” bits are transmitted as well as data, and sending that information uses some of the available bit-times.

Data packets and framing

Any node can be a bus master. If a node wishes to initiate communications, it pulls SDA low while leaving SCL high. Since any node can pull SDA low to start communications, a node must first check SDA to be sure it is high before initiating transaction. If a node begins sending data, and tries to transmit a logic 1 but SDA will not float high, that indicates some other node is driving the bus, and the current transaction must abort, wait for a time, and try again later.

After SDA is pulled low to start a transaction, the master pulls SCL low to initiate a clock pulse. Except for the start and stop bits, SDA can only change when SCL is low. While SCL is held low, SDA is pulled low (for a 0 data bit) or allowed to float high (for a 1 data bit), and then when SDA is stable SCL is allowed to float high. Once SCL is high, the master waits a minimum of 4us (for standard speed) to give the slave time to record the bit, and then drives SCL low again so a new bit value can be driven on SDA.

Figure 2. I2C is a multi-master, multi-slave bus
Figure 2. I2C is a multi-master, multi-slave bus

The initial 8 bits transmitted by the master include a 7-bit slave address and a single bit to indicate whether the master will write data to a slave or read data from a slave. If the addressed slave exists on the bus, it will respond by driving SDA low to send an ACK bit back to the master. If no slave exists for the address that was sent, the SDA line remains high. After receiving the ACK bit, the master will begin sending bytes if it is writing to the slave, or begin receiving bytes if it is reading from the slave. Either way, the master drives SCL at the proper frequency.

Figure 3. I2C data packet
Figure 3. I2C data packet

If the master is writing, it takes a short break every 8 bits so the slave can send an ACK (a 0 bit) to confirm it is receiving data. If the master ever sees a 1 ACK bit, then the slave is signaling it is unable to accept data for some reason and the transaction terminates. If the master is reading from the slave, then the slave will pause every 8 bits and the master must respond with an ACK.

The master may send or receive any number of bytes – the content and meaning of the message sent or received is defined by the particular device. A typical message might have a “header” that includes addresses or commands, followed by data. But there is no standard, and each device is responsible for its own protocol.

At the end of a message, the master sends a “stop bit” by setting SDA low, letting SCL float high, and then letting SDA float high (recall SDA can only change when SCL is low for a normal data bit). After sending the stop bit, the master releases the bus and any master can start a new transaction. The master can also send a “repeated start” without releasing the bus by setting SDA high, letting SCL float high, and then driving SDA low again.