LSM9DS1 Inertial Module

Overview and use of Blackboard's ST LSM9DS1 9-axis inertial module



The Blackboard includes an LSM9DS1 “iNemo” multi-sensor package that contains a 3-axes accelerometer, gyroscope, and Magnetometer (compass). The iNemo device has both an SPI and I2C port, but the Blackboard communicates using only SPI (note: the iNemo pins routed to the ZYNQ can be configured for use as I2C signals, but the Blackboard_Standart_Config HDF file uses only SPI0).

The Blackboard uses SPI0 to communicate with the LSM9DS1. The SPI bus signals are routed through ZYNQ’s FPGA using the EMIO interface, which makes no difference to the ARM software – the SPI port can be used normally, without any awareness that the FPGA is involved. The signals are routed through the FPGA because too few “dedicated PS” pins (called MIO pins) were available, and also routing signals through the FPGA makes it is possible to create additional hardware features, or even a separate SPI IP core.

Figure 1. LSM9DS1 top-level block diagram

ZYNQ - LSM9DS1 Interface

The LSM9DS1 actually uses two SPI ports to communicate with its on-board instruments. The two ports each have their own SS and MISO signals, but they share SCLK and MOSI signals. The accelerometer and gyroscope share one port selected with SS0, and the magnetometer uses the second port, selected with SS1. Because the Blackboard routes ZYNQ’s SPI1 bus through the FPGA, FPGA logic can be used to seamlessly merge the two MOSI signals (a mux passes MOSI from the accelerometer/gyro whenever SSO is asserted, otherwise MOSI from the magnetometer is passed through). The SPI controller sees both SPI busses as completely independent - when SS0 is active, MISO comes from the accelerometer/gyro, and when SS1 is active, MISO comes from the magnetometer, and so the SPI controller always receives the correct data. From a programmer’s perspective, SS0 must be manually set in an SPI control register to access the accelerometer/gyro, and SS1 must be manually set to access the magnetometer (see the SPI document for more information). The ZYNQ SPI controller allows up to three SS signals per SPI controller, and only one can should asserted at any given time.

The LSM9DS1 contains around 50 internal registers for accelerometer/gyro setup, control, and data (accessed using SSO), and another 20 or so for the magnetometer (accessed using SS1). Some of the most useful registers are discussed below – refer to the LSM9DS1 data sheet on for complete information.

Accelerometer/Gyro registers (SS0)

Since there are 50+ registers available, the first byte sent is used to specify the address of the intended register, and also whether a read or write cycle is underway. For the accelerometer/gyro, the first SPI bit sent in any transaction defines a read (1) or write (0) transaction, and the next seven bits define the intended register’s address. All registers are 8 bits, but many data elements are 16 bits. 16-bit data is stored in two consecutive 8-bit registers that can be configured as one 16-bit register, so a single SPI transaction can be used (with a single address) to read 16 data bits, instead of two back-to-back 8-bit transactions. A bit in the control register is set to allow 16-bit transactions by default – this bit can be reset to force 8-bit transactions.

All SPI transactions use 16 or 24 bit clocks. The first 8 clocks (i.e., the first byte) define whether a read/write status and the register’s address – that means the “payload” is either one or two bytes. For a write transaction, the next one or two bytes are the data to be written. Note that writing to the SPI bus will shift data from the MISO pin into the read FIFO – this data is meaningless, and should be ignored (or flushed from the FIFO).

A read transaction requires one byte to be written to define the address and read/write status, and then one or two bytes of “dummy data” to cause data produced by the accelerometer/gyro to be shifted out. This dummy data required for a read operation is only used to shift data out, and it will be ignored by the LSM9DS1 (typically, all 0’s are shifted in). Also, shifting in the first byte to define the address and read/write status will cause 8 bits to be shifted out. These first 8 bits will contain the R/W and address bits form the previous transaction, and can be ignored.

The table below shows some of the often used registers by the accelerometer/gyro. For a complete list of all registers and their functions, refer to the LSM9DS1 data sheet.

Figure 2. Acceleromoter/Gyro Important Registers

There are several configuration registers in the accelerometer and gyroscope, but the default values are probably adequate for most applications. Only CNTRL_REG1 and CNTRL_REG6 must be configured to start the instruments. Writing a 0xA0 to both registers will start both instruments with a data rate of 467Hz.

Magnetometer registers (SS1)

As with the accelerometer/gyro, the magnetometer uses the first byte of any SPI transaction to define the register address and read/write status. The magnetometer differs slightly – it uses only 6 address bits, and so one bit can be used for another purpose. The first bit sent is the read/write status bit, and the second bit enables auto-increment for two-byte transfers. The remaining six bits define the register’s address. The table below shows some of the most often used magnetometer registers.

Figure 3. Magnetometer Important Registers

As with the accelerometer/gyro, there are several configuration registers for the magnetometer, but only one must be configured. Setting the lower two bits in control register 3 to “00” will enable continuous conversion.