ZYNQ timer/counter

Using ZYNQs timer/counter to create an accurate time base

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In order to process, record, or produce information on a precise time schedule, a processor must have access to an accurate time base. The most accurate time base is typically derived from a counter that runs continuously for as long as power is applied. To measure time as precisely as possible, the counter increments using the fastest clock possible.

The ZYNQ chip provides a 64-bit global timer module for this purpose. On the Blackboard, the global timer module uses a 333MHz clock. Once started, it will count from 0 to 2^64, updating once every 3ns, for 1750 years (2^64 is a big number!). Applications can use the global timer to generate periodic interrupts, so that processing steps can be completed on a precise and accurate schedule.

For example, an analog-to-digital converter may need to be read every 10us. The processor could try to execute a timing loop to “burn” exactly 10us between reading the ADC, but it would be difficult to measure 10us exactly, and any errors in timing would introduce quantization errors into the sample data. In addition, a processor running at 500MHz would execute 5000 instructions in a timing 10us loop – a huge waste of resources! Using the global timer to measure 10us would result in a more accurate time base, and leave the processor free to do other tasks. You will use the global timer in the next project, and it will be more fully explained then.

In addition, many applications must produce periodic waveforms to control sensors, motors, or other external devices that need an accurate time base. Likewise, some applications must also accurately measure the timing of input signals that arise from sensors or other apparatus. In these time-critical situations, using a timer to generate an accurate time base without consuming processor cycles is the only solution that makes sense. The ZYNQ device also includes a timer/counter module to assist in creating or measuring periodic signals.

The triple-timer-counter (TTC) modules on ZYNQ use 16-bit counters and a programmable clock to create (or measure) periodic waveforms. The period and duty cycle of waveforms can be accurately and easily controlled by writing a few values to configuration registers. The output waveforms can be polled, they can generate interrupts, and they can be sent to the FPGA or off-chip to control IP blocks or external devices.

Triple Timer Counter (TTC) modules

The ZYNQ chip contains two TTC modules that each contain three independent timer/counters, for a total of six counters. A representation of one such counter is shown below. Each 16-bit timer/counter includes a 16-bit prescaler on its clock input, an interval register/comparator to set a regular counting interval, a zero-detect comparator, and three “match” register/comparators to compare the counter value to a given user-programmed value. The interval and match values can be used to create periodic waveforms, to generate interrupts, and to precisely measure input periodic waveforms.

Figure 1. ZYNQ's Timer/Counter Module IP Block
Figure 1. ZYNQ’s Timer/Counter Module IP Block

Each of the six counter modules include a 16-bit interval register. The interval register can be programmed with any 16-bit number, and each time the count value equals the value stored in the interval register the counter will reset back to zero and continue counting. If the interval resister contains zero, then the counter will count through the entire 2^16 count range, roll over, and continue counting. Each of the six counter modules also include three match registers. Each time the counter value equals one of the programmed match values, an interrupt can be generated. The first match register (match1) can also be used together with the interval register to create a periodic output waveform (see the PWM section below).

An output waveform from each counter module can be polled by software, or routed to an output pin or to the programmable logic section (the PL, or FPGA) for use by custom IP blocks. The counter can be configured to count up or down by setting the DEC bit in the configuration register.

Table 1 below shows the configuration registers for TTC0 counter 1; additional instances of these same registers exist for the other five counters (two in TTC0, and three in TTC1). The second table below shows the definitions for the bits in the clock configuration register, and the third table shows the bits in the counter configuration register.

Table 1. TTC0 Counter 1 Configuration and Status Registers (Base Address 0xF800 1000
Table 1. TTC0 Counter 1 Configuration and Status Registers (Base Address 0xF800 1000
Table 2. TTC Clock Configuration Bits
Table 2. TTC Clock Configuration Bits
Table 3. TTC Counter Configuration Bits
Table 3. TTC Counter Configuration Bits

An interrupt can be generated whenever the counter equals zero. If the counter is operating in interval mode (by setting bit 1 in the counter configuration register), it increments or decrements continuously between 0 and the value of the Interval register, with the direction of counting determined by the DEC bit (bit 2) of the Counter Control register. Otherwise the counter operates in overflow mode, and increments or decrements continuously between 0 and 0xFFFF (again with the direction of counting determined by the DEC bit of the Counter Control register). In either mode, an interrupt can be generated when the counter equals zero or when it equals one of the values programmed into the match registers.

The input clock to the timer module (PS_Clk) can come from the processor clock, or from the FPGA – the Blackboard is setup to use the 111.111MHz processor clock. The prescaler register divides the input clock by 2^(N+1), where N is the 4-bit prescaler value. The prescaler allows the 111.111MHz input clock to be divided by the first 16 powers of 2 (so, 2, 4, 8,… through 65,636).

Using the TTC to generate a PWM signal

Each counter can produce PWM signal using the interval and match1 values: the interval value sets the PWM window frequency, and the match value drives the waveform high or low at a given count value. If the CLK_POL bit (bit 1 of the counter configuration register) is set to a ‘1’, the output waveform will be: driven to a ‘1’ at the start of the interval; driven to ‘0’ when the counter value equals the match1 value; and driven back to ‘1’ when the counter resets to start a new interval. This is illustrated in the figure below. If CLK_POL is ‘0’, then the output waveform will start low, be driven high when the counter equals match1, and then reset back to low to start a new interval.

Figure 2. PWM signals and registers
Figure 2. PWM signals and registers

As an example, setting the 4-bit clock prescaler value to 9 will cause the counter to run at 111.111MHz/1024, or 108KHz. Then setting the interval register to 10000 will cause the counter to reset every 10000 counts, to create a PWM window frequency of 108KHz/10000, or about 10Hz. Then, the PWM duty cycle can be set by programming the match1 register. If CLK_POL is set to ‘1’, then any pulse width between 1 and 2^16 clock periods (about 10us per clock period based on the 10KHz clock) can be set, with the pulse going high at the start of the interval, and back low when the counter equals the match value.

To design a PWM signal for any given application, you must decide what “step size” or time resolution is required for each pulse length (i.e., at what precision can you adjust pulse widths), what PWM period (or window frequency) is required, and how many different pulse lengths per window are needed. These values are related: the PWM period divided by the minimum pulse length gives the number of possible pulses lengths that can be created. The smallest attainable pulse width defines the minimum quantity that the PWM signal can represent; the maximum number of pulses per window defines the maximum quantity the PWM signal can represent, and their ratio defines the “dynamic range” of the PWM signal (often, a PWM signal must be able to represent a signal with a given dynamic range). In the case of driving a servo motor, if the minimum PWM step size rotates the servo by one degree, and each pulse must be able to attain at least 180 lengths, and the PWM period is 20ms, then given the systems time base, values can be chosen for the main clock divider, the interval time, and the individual pulse widths. Since the main time base and divider ratios are not changeable (they are fixed on Blackboard/ZYNQ), you must choose “best fit” values for the main clock divider, interval time, and pulse widths.

Figure 3. PWM signal step size
Figure 3. PWM signal step size

A representation of one of the six counters that emphasizes the blocks needed to create a PWM signal is shown below. Blackboard’s hardware configuration file routes the waveform outputs of the three counters in TTC0 to the PWM pins on servo connectors J1, J2, and J3.

Figure 4. TTC block diagram highlighting blocks and functions for creating PWM
Figure 4. TTC block diagram highlighting blocks and functions for creating PWM