1. Digital Systems
2. Resource Document: APB Bus signals and Timing

The Advanced Peripheral Bus (APB)

The advanced peripheral bus was designed by ARM as a part of AMBA, the same family of buses AXI comes from.

Signals

• pclk: all APB signals are synchronous to this clock
• psel : master signals the peripheral it is being accessed
• penable : master signals the bus is in the access phase (2nd or later clock cycle)
• paddr[31:0] : signals the address being accessed by the bus master.
• pready : slave signals to the master it can complete the transaction
• pslverr : slave signals to the master a transaction error occured
• pwrite :master signals to slave a transaction is a write (if 0 transaction is a read)
• pwdata :write data from the master
• prdata :read data from the slave.

APB transactions:

transactions are divided into two phases. The setup phase is always the first clock cycle of any transfer. The bus master drives an address on the bus and drives the psel for the peripheral it wants to access. If the master is making a write it will also drive pwrite and place write data onto the bus.

The access phase takes place following the setup phase. It can be completed in one clock cycle but it can also be extended by the slave (for example if it needs to access slower memory). In the access phase the signal ‘penable’ will be driven until the transaction completes. The slave-driven ‘pready’ can be driven low until the slave is ready. Once penable and pready are driven at the same time, the access phase completes.

Write transaction:

setup phase:

Master drives address, and pwdata onto the bus. Master drives psel and pwrite high. (indicates slave is being selected for a write)

access phase:

master drives penable high. (indicates access phase) slave drives pready high if it can accept the write immediatly, otherwise it can insert wait states by driving pready low

Read transaction:

setup phase:

Master drives address onto the bus. Master drives psel high, pwrite low. (indicates slave selected for a read)

access phase:

master drives penable high. (indicate access phase) If slave is ready it places read data on prdata, drives ‘pready’ high. otherwise, slave inserts wait states by driving ‘pready’ low.

In both read and write transactions if the slave needs to indicate an error condition to the master, it can drive pslverr high at the end of the access phase

The pready and pslverr signals can be driven by a constant 1 and 0, respectively. This will force every transaction to be 2 clock cycles long with no errors.