Circuits that use binary numbers (busses) as inputs are typically too large to represent using truth tables, and too large to design using K-maps or even computer-based minimization programs. They must either be defined using behavioral Verilog, or they must be divided into smaller, simpler circuits that can be combined into an overall solution.
Consider for example a circuit that adds two 8-bit binary number inputs to produce an 8-bit binary number output. A truth table used to represent the behavioral requirements of this circuit would need (2 x 8), or 16 input columns to represent all 2^16 (= 65,536) possible input combinations, with the eight output columns showing the sum of the two 8-bit input numbers. Clearly, this truth table is far too large to produce in its entirety.
A problem like this can be attacked using a “divide and conquer” method know as bit-slice design. Following this approach, the overall design is divided into a collection of smaller circuits that each operate on a pair of bits, and then these bit-slice circuits are assembled into the overall n-bit circuit. The goal is to design just one circuit that operate on any pair of bits, and then to replicate that exact same circuit n times.
Designing a bit-slice circuit is a different task than designing the overall n-bit circuit, because the requirements are different for the bit-slices. For example, an adding circuit used in an 8-bit system does not need a carry-in or carry-out signal to produce an 8-bit result. But a one-bit “bit slice” circuit component used in a larger adder would need to receive a carry-in signal from its less significant neighbor, and it would need to produce a carry-out signal to pass to its more significant neighbor. Any inter-slice dependencies like this must be identified and included in the design of the bit-slice module. Dealing with these additional internal signals may require some additional thought and design effort (and possibly some additional logic gates) that may not have been needed in a non-bit slice design. But the additional effort and resources are a small price to pay for enabling a more practicable design approach.
In the adder example, since all bit slices are the same, the overall 8-bit circuit includes a carry-in to the bit0 slice, and a carry-out from the bit7 slice. These extra/unneeded signals result from the fact that the same bit slice circuit was used in all bit positions. In an 8-bit adder, the carry-in to the bit0 slice must be tied to GND, and the carry-out of the bit7 slice can be ignored, or used as the 9th bit of the result.
As a second example, consider an 8-bit comparator circuit that can compare the magnitudes of two numbers and produce less-than, equal, or greater-than outputs. A bit-slice design would need bit-slice components that can pass information between themselves, because no single bit slice can determine the overall relationship between the n-bit input numbers. Information from all bit slices must be combined to drive the overall circuit output, and that requires passing information between neighboring bit slices.
Many (most?) circuits that operate on binary numbers can be easily broken down into smaller, bit-wise operations. But some circuits defy this approach, and thought experiments or trial applications of possible bit-slice designs may not indicate any likely bit-slice solutions. Thus, the first goal in applying the bit-slice design method is to determine whether it is possible to express a given problem as an assemblage of bit-wise operations.
In bit-slice designs, consideration must be given to the operating speed of the overall circuit as well. Since bit-slice designs often must pass information from bit-slice to bit-slice, the delay between a change in operand bit0 and a resulting change on the most-significant result bit may be too long to be useful in any given circuit. The bit-slice design method is often the easiest way to solve a given n-bit bus circuit design problem, but it typically doesn’t result in the most efficient solution.