Defining and accessing temporary registers
When processor or digital circuit needs to temporarily store a relatively small number of data values (say, from 2 to 32), flip-flop based registers are often used. Flip-flop holding resisters are simple to define and use in a Verilog environment, but they consume lots of resources. If a greater number of data points need to be stored, more efficient and special-purpose memory circuits are often used (i.e., a single bit can be stored efficiently using a 6-transistor circuit, whereas flip-flops use 30 or more transistors). For this project, only eight 16-bit registers are needed, and their simplicity outweighs their inefficiency. When a group of registers are used to store temporary data values, they are typically organized and referred to as a register file.
A register file typically contains an address decoder to select which register is to be written, and an address mux to determine which register is to be read. Note that particular timings must be obeyed for both reading and writing. To compete a write cycle, the write address, a write enable signal, and the data value must be present at the appropriate clock edge. Likewise, to complete a read cycle, the data must be consumed while the read address is present.
A block diagram and sample Verilog code for a simple register file are shown below. Note the CLR signal is a synchronous clear, and RST is an asynchronous reset used only at start up.