Synthesize, Implementation, and Generate Bitstream

Tutorial on how to synthesize, implement, and generate bitstream for Vivado Projects

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Synthesize, Implementation, and Generate Bitstream for Vivado Projects

Synthesize

In Synthesize process, Verilog HDL codes are compiled and translated into netlist by a program called a synthesis tool. You can start Synthesize process by clicking on Run Synthesis button in the Flow Navigator panel, as highlighted in red in Figure 20.

When synthesis is running, select log panel which is located at the bottom of Project Manager. As the synthesis tool is running, the program will print out a lot of information about what the program is doing at the moment. All the errors occurring during the synthesis process are all described in the log.

Figure 1. Start Synthesis process and monitor the systhesis log
Figure 1. Start Synthesis process and monitor the systhesis log

Implementation

After the design is synthesized, you need to run the Implementation process. The implementation process maps the synthesized design onto the FPGA chip targeted by the design. Click Run Implementation button in the Flow Navigator panel, as highlighted in red in Figure 21.

When implementation is running, select log panel which is located at the bottom of Project Manager All the errors occurring during the implementation process are all described in the log.

Figure 2. Start Implementation process and monitor the implementation log
Figure 2. Start Implementation process and monitor the implementation log

Generate Bitstream

After the design is successfully implemented, you need to run Generate Bitstream located in the Flow Navigator panel, as highlighted in red in figure 22. The process translates the implemented design into a bitstream which can be downloaded onto your FPGA board.

Figure 3. Generate Bitstream
Figure 3. Generate Bitstream