# Flip-Flops

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## Flip-Flops

All useful memory devices need at least two inputs – a data input signal and a timing signal to control when the data signal is memorized. The output of a memory device is often referred to as the present state, and the input is called the next state. At each new assertion of the timing signal, the next state becomes the present state. In a D-latch, the next state input is tied directly to the present state output whenever the timing control input is asserted. But when the timing control is de-asserted, the present state becomes fixed and holds the value that was present on the next state when the timing signal was de-asserted. A D flip-flop modifies the function of a D-latch in a fundamental and important way: the next state (or D input) can only be written into the memory on the edge (or transition) of the timing signal.

A D flip-flop (DFF) is one of the most fundamental memory devices. It typically has at least three inputs, including a data input (usually called D) that defines the next state, a timing control signal (usually called clock) that controls when the data is memorized, and a reset input that forces the memory to be reset to ‘0’, regardless of the other two inputs. A DFF records (or registers) new data whenever an active clock edge occurs; the active edge can be either the rising edge or the falling edge. The clock signal is typically a regular, repeating square wave that continuously causes the DFF to memorize its data input signal at some frequency.

A rising-edge triggered (RET) DFF symbol uses a triangle to show that the flip-flop is edge-triggered; a falling-edge triggered (FET) DFF symbol uses the same triangle, but with a bubble on the outside of the bounding box (just like any other asserted-low input). The timing diagram below in Fig. 3 illustrates RET DFF behavior. Note that the Q output changes only on the active edge of the clock, and the reset signal forces the output to ‘0’ regardless of the other inputs.

As with the basic cells, a D flip-flop or D-latch can enter a metastable state if the data and control inputs are changed at exactly the same time. In a D-latch, the data must be stable when the control input is de-asserted. In a DFF, the data input must be stable for a time immediately before and immediately after the clock edge. If the data is not stable at the clock edge, a metastable state may be clocked into the memory element. If this happens, the memory element may not be able to immediately resolve to either low voltage or high voltage, and it may oscillate for a time. Thus, when designing circuits using edge-triggered flip-flops, it is important to ensure the data input is stable for adequate time prior to the clock edge (known as the setup time), and for a time after the clock edge (known as the hold time). Setup and hold times vary between several tens of picoseconds (for designs inside single IC’s) to several nanoseconds (for designs using discrete logic chips).

A schematic for a basic D flip-flop is shown in Fig. 5. Note the flip-flop is constructed from three basic cells. Two of the basic cells check for a rising edge, and the third memorizes the D input if a rising edge was detected. Several slightly different schematics can be found in various references, but any circuit called a DFF will exhibit the same behavior.

The DFF is the simplest and most useful edge-triggered memory device, and it can be used in any application that requires a flip-flop. Over the years, other types of flip-flops were designed and used as well, but they were really just D flip-flops with some added features. For example, the JK flip-flop used two inputs to direct state changes: the J input set the output to a ‘1’; the K input reset the output to a ‘0’; and if both J and K were asserted simultaneously, the output toggled between ‘1’ and ‘0’. Another device, the T flip-flop, simply toggled between ‘1’ and ‘0’ on each successive clock edge so long as the T input is asserted. These other flip-flops were commonly used in older digital systems (especially those built of discrete 7400 logic ICs) because their added features meant that fewer chips might be needed to construct a given circuit. But they offer no advantages to designs built using programmable chips (like the FPGA used on the Blackboard). Figure 6 below illustrates JK and T flip-flops.

#### Flip-flop with Asynchronous Reset

always @ (posedge(clk), posedge(rst))
begin
if (rst == 1)
Q <= 1'b0;	// Q is reset to 0
else
Q <= D;
end


#### Flip-flop with Combinational Logic

always @ (posedge(clk), posedge(rst))
begin
if (rst == 1)
Q <= 1'b0;	// Q is reset to 0
else
Q <= (A & B);
end