# Multiplexers

## Multiplexers

Data selectors, more commonly called multiplexers (or just muxes), function by connecting one of their input signals to their output signal, as directed by their select or control input signals. Muxes have N data inputs and $log2^N$ select inputs, and a single output. In operation, the select inputs determine which data input drives the output, and whatever voltage appears on the selected input is driven on the output. All non-selected data inputs are ignored. As an example, if the select inputs of a 4:1 mux are ‘1’ and ‘0’, then the output Y will be driven to the same voltage present on input I2.

Common mux sizes are 2:1 (1 select input), 4:1 (2 select inputs), and 8:1 (3 select inputs). The truth table in Fig. 1 below specifies the behavior of a 4:1 mux. Note the use of entered variables in the truth table if entered variables were not used, the truth table would require six columns and 26 or 64 rows. In general, when entered-variable truth tables are used to define a circuit, control inputs are shown as column-heading variables, and data inputs are used as entered variables. Figure 1. Truth Table, Logic Graph, and Block Diagram of a 4-to-1 Multiplexer

The truth table can easily be modified for muxes that handle different numbers of inputs by adding or removing control input columns. A minimal mux circuit can be designed by transferring the information in the truth table to a K-map, or by simply inspecting the truth table and writing an SOP equation directly. A minimal equation for the 4:1 mux is as follows (you are encouraged to verify that this is a minimal equation):

$Y = \overline{S1} \cdot \overline{S0} \cdot I0 + \overline{S1} \cdot S0 \cdot I1 + S1 \cdot \overline{S0} \cdot I2 + S1 \cdot S0 \cdot I3$

An N-input mux is a simple SOP circuit constructed from N AND gates each with $log2^N + 1$ inputs, and a single output OR gate. The AND gates combine the $log2^N$ select inputs with a data input, such that only one AND gate output is asserted at any time, and the OR output stage simply combines the outputs of the AND gates (you will complete the sketch for a mux circuit in the exercises). As an example, to select input I2 in a 4 input mux, the two select lines are set to S1 = 1 and S0 = 0, and the input AND stage would use a three input AND gate combining S1, not (S0), and I2.

Mux circuits often use an enable input in addition to the other inputs. The enable input functions as a sort of global on/off switch, driving the output to logic ‘0’ when it is de-asserted, and allowing normal mux operation when it is asserted. Figure 2 below shows the block diagram of mux with enable.

Larger muxes can easily be constructed from smaller muxes. For example, an 8:1 mux can be created from two 4:1 muxes and one 2:1 mux if the outputs from the 4:1 muxes drive the data inputs of the 2:1 mux, and the most-significant select input drives the select input of the 2:1 mux.

Muxes are most often used in digital circuits to transfer data elements from a memory array to data processing circuits in a computer system. The memory address is presented on the mux select lines, and the contents of the addressed memory location are presented on the mux data inputs (this application of muxes will be presented in later projects that deal with memory systems). Since most data elements in computer systems are bytes, or words consisting of 8, 16, or 32 bits, muxes used in computer circuits must switch 8, 16, 32 or more signals all at once. Muxes that can switch many signals simultaneously are called bus muxes. A block diagram and schematic for a bus mux that can select one of four 8-bit data elements is shown in Fig. 3 below.