Latches are the fundamental bi-stable memory circuit in digital systems to store data and indicate the state of the system. In this project, we are going to implement and simulate the basic NAND cell of an SR-Latch and see how it functions.
Figure 1 below shows an implementation for SR-Latch with NAND implementation. According to the truth table on the right, S and R are active low. When only S is asserted (S is ‘0’), the output Q is SET to ‘1’. When only R is asserted (R is ‘0’), the output Q is RESET to ‘0’. When neither S and R are asserted, the output holds its previous value.
SR-Latch is a kind of bi-stable circuit. However, due to propagation delay of NAND gate, it is possible to drive the circuit into metastable state, where the output is oscillating between 0 and 1. The metastable state will be triggered when neither the set operation nor the reset operation propagates through the whole cell before the cell changes to the hold state.
Step 1: Implement the Circuit in Verilog
Assume the NAND gates in SR-Latch have a delay of 1 ns.You may want to try to create the verilog file without looking at the example code, you can write the code based on figure 1 NAND cell and then check your work by clicking Show/Hide Code. The Verilog file for the SR-Latch looks like follows:
module sr_latch( input S, input R, output Q, output Qn ); wire Q_int, Qn_int; assign #1 Q_int = ~(S & Qn_int); assign #1 Qn_int = ~(R & Q_int); assign Q = Q_int; assign Qn = Qn_int; endmodule
Step 2: Create a Test Bench for the AND Cell SR-Latch
For the purpose of demonstrating the functionality of SR-Latch, we consider the following input simulus:
|0ns||De-assert both inputs|
|500ns||Assert both inputs|
|600ns||De-assert both inputs|
|700ns||Assert both inputs|
The code in the test bench looks as follows:
initial begin // Initialize Inputs S = 1; R = 1; // Add stimulus here #100 S = 0; #100 S = 1; #100 R = 0; #100 R = 1; #100 S = 0; R = 0; #100 S = 1; R = 1; #100 S = 0; R = 0; #100 ; end