XADC

Using ZYNQ's Analog to Digital Converter

1449

The ZYNQ chip includes dual 1MSPS, 12-bit analog-to-digital converters and several on-chip sensors for checking die temperature and power supply voltages. These circuits are located in the XADC circuit block, and the XADC block is part of the FPGA (not the ARM system). Like all other peripherals, the XADC block must be accessed through the AXI bus. But since the XADC block is a “hard macro” that is not a part of the ARM system, it’s register addresses must be assigned by the user. To do this, the XADC block could be instatiated in your Verilog source file, and the addresses could be assigned there. But, to make the task a bit simpler, Xilinx provides a Wizard that can be used to configure the XADC (see Xilinx document PG091 available at the link below). The Blackboard configuration file that we have been using (the .hdf file) configures the XADC block for you, and makes the registers available at base address 0x4BB06000.

ZYNQ XADC Wizard “LogiCOPE IP Product Guide”: XADC Wizard

Figure 1. XADC Block
Figure 1. XADC Block

A table on pages 16-23 of the XADC Wizard describes all 83 registers that are available in the XADC block. Registers include reset functions, channel selection, various setup and control functions, and several data registers for the ADC conversion results and sensor outputs. (Note: channel selection refers to the 16-channel analog mux on the ADC input, which is included so that up to 16 signals can be digitized without the need for an external mux.) Only a few of the data registers are of interest here, and these are shown in the table below (the offset values in the table must be added to the assigned XADC base address of 0x4BB06000). You can read about the rest of the registers in Xilinx document UG091.

Figure 2. Some XADC Registers
Figure 2. Some XADC Registers

All data registers are 16 bits, but only the most significant 12 of the 16 bits are used. Since the ARM uses 32 bit address, these 12 unused bits are in the upper bits of the least-significant two bytes.

Figure 3. 12-bit "raw" XADC data
Figure 3. 12-bit “raw” XADC data

The XADC supports oversampling to create a sample with more than 12 bits. These extra bits are manufactured by averaging several points together to produce a single sample point with more significant bits. The hardware design included in Blackboard’s .hdf file can configure the XADC to read 256 “raw” data points, and combine them into one 16-bit sample. With this feature enabled, all 16 bits in the lower part of the data word contain usable bits.

Figure 4. 16-bit data after bits manufactured through averaging
Figure 4. 16-bit data after bits manufactured through averaging

The XADC can sample an intenal temperature sensor to rmeasure the die temperature. The 16-bit temperature code can be read from register 0x200, and the data value must be mapped into the centigrade temperature range (-273 - +230) by multiplying the ADC code by a scalar (503 / 65536), and then subtracting 273 to shift the result to the proper range. So a code of 0x9770 (which is 38768 decimal) would equal 38768 * 503/65536 - 273, or about 25C.

The XADC can also sample all on-chip power supplies - see the register table in PG091 for more information.

The voltage on the main external ADC input is available by reading register 0x20C. On the Blackboard, this input is connected to a 10K potentiometer connected between 0V and 1V. To map the ADC code to a voltage, the code must be multiplied by 1/65536.