Mux and Demux Communication System

Introduction wrappers in Verilog.

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Step 1: Create a New Project

Create Vivado project as in previous projects.

Step 2: Implement a 4-to-1 Multiplexer

Create a 4-to-1 Multiplexer named mux that will pass one of the four inputs I[3:0] to output Y based on the select signals S[1:0]. You can use the mux you designed in the previous project.

module mux(
    input [3:0] I,
    input [1:0] S,
    output reg Y
);

// Your behavioral description of Y
// using if-else or case statements

endmodule
Figure 1. Block Diagram for 4-to-1 Multiplexer.
Figure 1. Block Diagram for 4-to-1 Multiplexer.

Step 3: Implement a De-Multiplexer

A de-multiplexer is a binary decoder with an enable signal. The functional definition of a binary decoder with an enable signal is shown in Fig. 2.

module demux(
    input EN,
    input [1:0] I,
    output reg [3:0] Y
);

// Your behavioral description of Y
// using if-else or case statements

endmodule
Figure 2. Decoder with an enable signal as a de-multiplexer
Figure 2. Decoder with an enable signal as a de-multiplexer

You may use case statement or an if-else statement within an always block to describe the behavioral of the circuit. If needed, refer to PROJECT 4.1: Multiplexer, Decoder, Encoder, and Shifter.

Step 4: Design the top-level Verilog module

The top level module instantiates and connects the mux and demux subcircuits to create the overall top-level design. A system diagram is shown in Fig. 3 below. The input/output ports of the module wrapper are shown in green; the input/output ports of the mux and demux modules are in black; and an internal wire is shown in purple.

Figure 3. Block Diagram of Top Level Module Wrapper
Figure 3. Block Diagram of Top Level Module Wrapper

Create a new Verilog module file named wrapper (or any other suitable name) with 4 data inputs sw[3:0]; two select inputs btn[1:0]; and four outputs led[3:0].

module wrapper (
    input [3:0] sw,
    input [1:0] btn,
    output [3:0] led
);

// Structural Description of wrapper

endmodule

The top-level module needs one internal signal called sdata which carries the time-multiplexed signal between the mux and demux block. Internal, non-“port” signals must be declared as a type wire before they can be used in the module. The declaration of internal signals should be placed after the input and output declaration.

wire sdata;

After the internal signal/wire declaration, the mux and demux circuits can be instantiated. Any Verilog module can be used (or “instantiated”) in any other Verilog module by including it’s name, and then listing how the signals whould be connected. The example code below shows how the mux circuit can be instiated in the top-level “wrapper” module. Note the syntax for connecting the lower-level mux signals to the higher-level wrapper signals: the lower-level signal name is listed first, preceed with a “.”, and then the higher-level signal it maps to is shown in parenthesis.

mux input_mux (
    .I(sw),
    .S(btn),
    .Y(sdata)
);

Similarly, the demux circuit can be instaitated and connected as shown in the block diagram.

demux output_demux (
    .EN(sdata),
    .I(btn),
    .Y(led)
);

Your “wrapper” Verilog source file should look like this:

module wrapper(
    input [3:0] sw,
    input [1:0] btn,
    output [3:0] led
);

wire sdata;

mux input_mux (
    .I(sw),
    .S(btn),
    .Y(sdata)
);

demux output_demux (
    .EN(sdata),
    .I(btn),
    .Y(led)
);

endmodule

Step 5: Create an XDC File and Generate Bitstream

Now, create an XDC file and generate the bitstream file.