A first look at Verilog

The basics of Verilog modules

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Verilog Signals

As long as power is applied, output signals from digital circuits are always driven to a ‘0’ or a ‘1’ depending on the circuit inputs. Combinational circuit outputs can be driven to a new value immediately after an input changes, but memory circuit outputs can only be driven to a new value after a change on a clock or reset signal. In Verilog, combinational logic output signals are said to be “continuously driven”, meaning they take new values immediately after input changes. Any time any signal changes in a Verilog simulation, all combinational circuits that use that signal as an input are immediately simulated, and their outputs are updated as needed. Memory outputs do not take on new values immediately after their data inputs change; rather, their outputs can change only after a change on a clock or reset signal. The Verilog simulator must follow a procedure, and check for a change on clock or reset before assigning a new output. Memory outputs are said to be “procedurally driven”, meaning they can only take new values after the simulation procedure of checking for an edge on a clock or reset signal.

Verilog Modules

Verilog source files use “modules” to define all circuits, and the module statement is the first line of code in a Verilog source file. The module statement names the module so it can be accessed by other designs and tools as needed, and it defines all input and output signals. When writing “Behavioral Verilog” code, the module statement is followed by any number of continuous assignment or procedural assignment statements to define the circuit’s behavior. When writing “Structural Verilog”, the module statement is followed by any number of instantiations of other modules. In practice, smaller and simpler circuits typically use behavioral Verilog, and more complex circuits, or those that reuse previously written modules, use structural Verilog. Many examples of behavioral and structural Verilog circuit descriptions are provided in upcoming projects.

Verilog Types and Signal Assignments

Verilog source files define how signals are driven over time. Two data/signal types are used – the “wire” type for continuously driven signals arising from an input pin or a combinational logic circuit; and the “reg” type for procedurally driven signals that (usually) arise from a memory circuit.

Continuous assignment statements drive “wire” signals, and so continuous assignment statements define combinational logic circuits. They begin with the keyword “assign” followed by the output signal name, and then the conditions under which the output is driven.

Procedural assignment statements drive “reg” signals, and so procedural assignments are used to define memory circuits. They begin with the keyword “always” that identifies a procedural block the simulator must always execute (to see if a clock or reset signal has occurred). Procedural assignments will be discussed later.

Input signals to modules are always type “wire”; output signals from modules can be type “wire” or “reg”. If additional wire or reg signals are needed inside a module (for example, to transport signals between assignment statements), they must be explicitly declared after the module statement (see figure 3 below).

Three Verilog examples are provided below. More discussion and examples are in the first few Digital Logic projects, and in the presentation slides. The general format of Verilog circuit descriptions are shown below.

Verilog overview presentation slides

Figure 1. A simple Verilog example
Figure 1. A simple Verilog example
Figure 2. Another simple Verilog example
Figure 2. Another simple Verilog example
Figure 3. A Verilog example with a declared wire
Figure 3. A Verilog example with a declared wire