1. Digital Logic
2. Tutorial: Guess the Logic

Introduction

In this tutorial, you will download a bit file to your board in order to configure the Zynq with four different logic circuits. The circuits use buttons and switches for inputs, and LEDs for outputs. You must probe the logic circuits by applying all possible combinations of input signals. From the results of applying all possible combinations, you will be able to write logic equations that describe the circuits’ behaviors. You will then rewrite the equations using Verilog HDL, which will re-implement them on the FPGA and compare the circuit behavior with the given bit file.

Zeros and Ones

A signal in a digital circuit is a circuit net that transports an output voltage from one device to one or more input connections of other devices. In a digital circuit, signals are constrained to be at one of two voltages, either Vdd (1) or GND (0). Thus, all data in digital circuits can only be represented as a zero or one for the two available states. Systems that use two-state data are known as binary systems, and a two-state signal is a binary signal. One signal wire in a digital circuit can carry one binary digit (abbreviated to bit) of information. Conventionally, we assign symbol “1” to true and “0” to false. For example, an AND relation can be logically described as “true” when all of the inputs are “true.” Using the binary numbers assigned to a digital system, the logical AND truth table appears below:

A	B	F
0	0	0
0	1	0
1	0	0
1	1	1

Step 1: Download the Bitstream and Program your Blackboard

Download the Bitstream

Click the button to obtain the pre-compiled bitstream file for Blackboard: Blackboard_P2.Zip

Program Your Board With the Bitstream File

Decompress the zip file and program your board with Hardware Manager. You do not need to create a project for this task. There is a Open Hardware Manager button on the first page when you open your latest version of Vivado. Then autoconnect the device, Program Device, and choose the downloaded bitstream file as the path.

Step 2: Fill out the Truthtable

Circuit I

The first circuit takes two slide switches SW0 and SW1 as inputs and uses LED LD0 to indicate the output of the logic function. As there are two inputs for this logic circuit, there are four possible combinations. According to the circuit of the switch, when the switch slides on, a high voltage (i.e., a logic “1”) will be presented on the input of the circuit. Similarly, if the LD0 turns on, a high voltage is presented on the output of the circuit, which means the current output of the logic circuit is a logic “1”. So we have both SW0 and SW1 off and we will need to check the LD0 status to fill out the first line of the truth table below. Slide the SW0 on to fill out the second row. Slide the SW0 off and SW1 on to fill out the third row. Slide both of them on to fill out the final row. After you fill out the truth table, you can click button “Check Result” to see if you filled it all out correctly.

SW1	SW0	LD0
0	0
0	1
1	0
1	1
Reset Check Result

Circuit II

The second circuit takes 3 slide switches SW1, SW2 and SW3 as inputs, and one LED LD1 as output. Probe Circuit 2 the same way you did Circuit 1 and fill out the truth table below. After you fill out the truth table, you can click button “Check Result” to see if you filled it out correctly.

SW3	SW2	SW1	LD1
0	0	0
0	0	1
0	1	0
0	1	1
1	0	0
1	0	1
1	1	0
1	1	1
Reset Check Result

Circuit III

The second circuit takes 4 slide switches SW4, SW5, SW6, and SW7 as inputs, and one LED LD2 as output. Probe Circuit 3 the same way you did Circuit 1 and 2, and fill out the truth table below. After you fill out the truth table, you can click button “Check Result” to see if you filled it out correctly.

SW7	SW6	SW5	SW4	LD2
0	0	0	0
0	0	0	1
0	0	1	0
0	0	1	1
0	1	0	0
0	1	0	1
0	1	1	0
0	1	1	1
1	0	0	0
1	0	0	1
1	0	1	0
1	0	1	1
1	1	0	0
1	1	0	1
1	1	1	0
1	1	1	1
Reset Check Result

Basic Logic Operations and Their Representations

AND, OR, and NOT (or inversion) are the three primary logic relationships that can be used to express any logical relationship between any number of variables. These simple logic functions form the basis for all digital electronic devices, from a simple microwave oven controller to a desktop PC. There are a set of symbols that are commonly used to express these logic operations. You may have seen some of the symbols in your math classes or in other programming languages. Table 1 represents symbols for three primary logic relationships:

Table 1. Comparison of Symbols of Three Primary Logic Relationships

Logic Operation	Mathematics	Real Digital®’s Website	C Programming Language	Circuit Schematic	Verilog HDL
A and B	$A\cdot B$ $A \land B$ $A \& B$	$A\cdot B$	A&B		A&B
A or B	$A \vee B$ $A + B$ $A \vert B$	$A+B$	A | B		A | B
Not A	$\lnot A$ $\sim A$ $!A$ $A'$ $\overline{A}$	$\overline{A}$	~ A		~ A

Sum Of Product (SOP) and Product of Sum (POS) Circuit

A product term is defined as an AND relationship between any number of variables, and a sum term is defined as an OR relationship between any number of logic variables. Any logic system can be represented in two logically equivalent ways: as the OR’ing of AND’ed terms, known as the sum of products (SOP) form; or as the AND’ing of OR’ed terms, known as the product of sums (POS) form.

A logic equation (and therefore a logic circuit) can easily be constructed from any truth table by applying the rules presented below.

Sum of Product (SOP)

• A circuit for a truth table with N input columns can use AND gates with N inputs, and each row in the truth table with a “1” in the output column requires one N-input AND gate.
• Inputs to the AND gate are inverted if the input shows a “0” on the row, and not inverted if the input shows a “1” on the row.
• All AND terms are connected to an M-input OR gate, where M is the number of “1” output rows.
• The output of the OR gate is the function output.

Product of Sum (POS)

• A circuit for a truth table with N input columns can use OR gates with N inputs, and each row in the truth table with a “0” in the output column requires one N input OR gate.
• Inputs to the OR gate are inverted if the input shows a “1” on the row, and not inverted if the input shows a “0” on the row.
• All OR terms are connected to an M-input AND gate, where M is the number of “0” output rows.
• The output of the AND gate is the function output.

Step 3: Re-implement the Logic Function Using Verilog HDL

Create a New Project

Create a new project in Vivado. You may refer to TUTORIAL: CREATE A VIVADO PROJECT for the detailed steps.

Create Verilog Source File

Create a new Verilog source file and add it to your project. Declare eight switches as inputs and three LEDs as output. Your Verilog code should look similar to the one below:

`timescale 1ns/1ps;
// Comment

module top (
    input [7:0] sw,
    output [2:0] led
);

endmodule

Add Design Constraints

Create a xdc file and add physical constraints of switches and leds (inputs and outputs of your Verilog module). You can review

Implement Circuit I

We will construct the logic equation in SOP form for demonstration. In Circuit 1, we have two rows (second row and third row) that shows a “1” in the output. So we need an OR gate with two inputs that generate the output, and two 2-input AND gates that provide the input for the OR gate. In the second row, input SW0 shows a “1” and input SW1 shows a “0”. So SW0 is connected to the input of the first AND gate and SW1 is inverted before connecting to the second input of the AND gate, as shown in the first product term in the equation. In the third row, input SW0 shows a “0” and input SW1 shows a “1”. So SW0 is inverted before connecting to the input of the second AND gate and SW1 is connected directly to the second input of the AND gate, as shown in the second product term in the equation. The output LD0 is the summation of these two product terms.

$LD0 = SW0 \cdot \overline{SW1} + \overline{SW0} \cdot SW1$

In Verilog HDL, this circuit is implemented as follows:

assign led[0] = (sw[0] & ~sw[1]) | (~sw[0] & sw[1]);

Implement Circuit II

imilar to Circuit 1, you can come up with the logic function for the second circuit in SOP form as:

$LD1 = \overline{SW3} \cdot \overline{SW2} \cdot \overline{SW1} + \overline{SW3} \cdot SW2 \cdot SW1 + SW3 \cdot \overline{SW2} \cdot SW1$

In Verilog HDL, we have:

assign led[1] = (~sw[3] & ~sw[2] & ~sw[1]) | (~sw[3] & sw[2] & sw[1]) |
    (sw[3] & ~sw[2] & sw[1]);

Implement Circuit III

Similar to Circuits 1 and 2, you can come up with the logic function for the second circuit in SOP form as: $LD1 = \overline{SW7} \cdot \overline{SW6} \cdot \overline{SW5} \cdot SW4 + \overline{SW7} \cdot \overline{SW6} \cdot SW5 \cdot SW4$

$+ \overline{SW7} \cdot SW6 \cdot \overline{SW5} \cdot \overline{SW4} + SW7 \cdot SW6 \cdot SW5 \cdot SW4$

In Verilog HDL, we have:

assign led[2] = (~sw[7] & ~sw[6] & ~sw[5] & sw[4]) | (~sw[7] & ~sw[6] & sw[5] & sw[4]) |
    (~sw[7] & sw[6] & ~sw[5] & ~sw[4]) | (sw[7] & sw[6] & sw[5] & sw[4]);

Step 4: Add Design Constraints and Generate Bitstream

Create an xdc file and add physical constraints of switches and leds (inputs and outputs of your Verilog module).

Then, click Generate Bitstream and Vivado software will automatically run the synthesize, implementation, and bitstream generation one after another.