Project 8 Counters, Clock Dividers, and the Seven-Segment Display

Measuring time and Creating Derivative Clocks

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Introduction

This project continues exploring sequential circuits, building on the foundational concepts and devices that were introduced in a previous module. In this project, several sequential components like counters and registers are presented. These circuits can be used by themselves to solve certain problems, but they are more typically used as components in larger, more involved sequential designs.

Measuring and managing time accurately is one of the most fundamental tasks in a digital system. Time is measured by electronic circuits that are stabilized by the resonant oscillations of quartz crystals or silicon oscillators. These highly stable and repeatable mechanical vibrations are used to create a reliable “master clock” signal that can be routed to the various IC’s in a digital system. Clock management circuits inside a given IC use the input clock signal to drive counters that measure time intervals and/or produce derivative clock signals.

This project presents various counter circuits that can accurately measure time intervals, and clock divider circuits that can be used to produce new clock signals that are derivatives of the input “master clock” signal.

Before you begin, you should:

  • Know Vivado, how to write testbenches, and how to use the simulator;
  • Know how to describe memory devices in Verilog.

After you’re done, you should:

  • Know how to describe counters in Verilog;
  • Understand clock dividers and how to design them;
  • Understand procedural statments in Verilog.

Background

Counter circuits are some of the most basic sequential circuit blocks. Clock dividers use counters to create new lower-frequency clock signals by driving the new clock signal low for some number of input clock cycles, and then high for some number of clock cycles. The topic documents provide background information and Verilog code examples for various counters and dividers.

The master clock on the Blackboard is 100MHz, which is far too fast for working with human-interface devices like LED displays. Any design that works with general purpose inputs and outputs (like switches and LEDs) will need one or more clock dividers.

Requirements

1. Design a clock divider based on an asynchronous counter

Create a clock divider that uses a structural asynchronous counter built from Xilinx flip-flop primitives. The counter uses the main Blackboard 100Mhz clock as an input, and it should generate a clock signal below 1Hz to drive the LED (hint: see the Asynch Divider topic document)

2. Design a clock divider based on a synchronous binary counter

Define a 28-bit synchronous binary counter that uses the 100MHz clock, and a second 4-bit counter that uses one of the bits from the 28-bit counter as a clock. Select a bit from the 28-bit counter that toggles at about .5Hz to use as a clock for the 4-bit counter. Connect the 4-bit counter outputs to four LEDs. Configure your Blackboard, and verify the LEDS toggle at the correct rate.

3. Counter Based Clock Divider

Create a counter/clock divider to produce a 1KHz output clock from a 100MHz input clock. Create a second clock divider that produces a 1Hz output clock from a 1KHz input clock. Connect the 1Hz output to an LED and verify it flashes at 1Hz.

4. BCD Counter

Create a 4-bit decimal (BCD) counter that continuously counts 0-9. Drive the counter from the 1Hz clock, connect its outputs to one digit of the 7seg display, and verify it counts through all digits at a rate of one digit per second. (Note: you need to place a seven-segment decoder between the BCD counter and the seven-segment display cathode signals).

5. 4-digit BCD Counter

Drive the 4-digit seven-segment display from a 4-digit decimal counter. To create the counter, connect four BCD counters together so that each digit increments at the correct time (D0 should increment at every clock edge, D1 should increment each time D0 reaches 9, D2 should increment each time D1 and D0 reach 9, and D3 should increment only when D0, D1 and D2 all reach 9). Then, build a 4-digit seven-segment controller system using a 4:1 4-bit bus mux, 2:4 decoder, and 2-bit counter. Connect the 4-digit decimal counter outputs to the seven-segment display controller, drive the counter from the 1KHz clock, and verify the counter counts through its range every 10s. See “seven segment” the background topic document for more information.

Challenges

1. 4 Digit Counter Controller

Change the 4-digit counter clock to a 1Hz clock, and make the count value loadable from the slide switches. Connect SW0 to counter enable, so the counter only counts when SW0 is a 1 (so, SW0 selects between “run mode” when SW0 = “1”, and “load mode” when SW0 = “0”). Then, connect SW1 and SW2 to a decoder that will select which counter digit to load, and use SW4-SW7 to set a count value into the digits. Verify your circuit works.