# Project 6 Delays in Logic Circuits

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## Introduction

So far, we have assumed that the circuit nodes in a digital circuit can switch state instantaneously, transitioning from 0 -> 1 or 1 -> 0 with no elapsed time. But this is not really the case – some amount of time is always required for any circuit node to change state. When a digital signal passes through a logic gate, it switches transistors on or off to drive the output node to a given state. The output circuit node (like all circuit nodes) has some amount of capacitance, and that capacitance must be charged or discharged for the node to change state. When the output changes state, the charge trapped on the output node must flow to one of the power rails, and this takes time.

The time required to charge or discharge output nodes can be lumped into a single “gate delay”. Although small, gate delays cannot be ignored. This project examines the sources of such delays, their possible detrimental effects, and what actions can be taken to minimize their impact.

#### Before you begin, you should:

• Know Vivado and how to use the Boolean board;
• Know how to design and implement logic circuits based on truth tables;
• Be able to describe a digital circuit in Verilog;
• Know how to write and run Verilog testbenches.

#### After you’re done, you should:

• Understand how hazards and glitches are formed;
• Know how to simulate a circuit with delays to illustrate glitches and other timing issues;
• Know how to modify a circuit to remove glitches.

## Background

Signal delays through combinational circuits are unavoidable. When a circuit node changes state, charged particles must be transported to or from the node, and this requires some amount of time. The topics develop this idea further, and the requirements illustrate the phenomenon in actual circuits.

## Requirements

#### 1. Illustrate the formation of a glitch in the simulator.

Follow the tutorial to simulate and illustrate the formation of a glitch:

#### 2. Change the OR Gate Delay and resimulate

Assume the OR gate in the previous circuit has a propagation delay of 2 ns. Simulate the circuit again and try to find the glitch. If there is a glitch, when does it occur and what is the duration of the glitch? If there is no glitch, can you explain why? Think about the differences in path delay for signal B. Also, think about how the Vivado Simulator works.

#### 3. Change the Delay of All gates and resimulate

Assume the delay of all gates are 5 ns. Modify the `CombCirc` module and the test bench properly and try to find the glitch. If there is a glitch, when does it occur and what is the duration of the glitch? If there is no glitch, can you explain why?

## Challenges

#### 1. Delay in Decoder

When your Verilog code is synthesized, it is “mapped” onto the available resources in the FPGA. Whatever the mapping may be, when your circuit is programmed into the FPGA there will be real, physical delays on all circuit nodes. During the synthesis process, the synthesizer tool produces a very accurate estimation of what the actual delays will be when your circuit is programmed into the FPGA. You can cause the simulator to use those delays, so that you can see their effect in the simulator output waveforms.

Create a 4:16 decoder, and connect the 16 outputs to the 16 LEDs on the Boolean board. Connect the four inputs to slide switches SW0-SW3, and verify your circuit works.

Then, armed with Google, the Vivado help resources, and your own tenacity, find the maximum delay between toggling SW0 and LED0 reacting to the change on SW0. Hint: The Xilinx tools produce a delay report - you can run the simulator with delays active, and Vivado will report delays for all circuit nodes. Vivado also includes a timing analyzer tool that you can use to specify the circuit paths you are interested in examinging more closely. Using these resources, you can identify net names, and find how much total delay there is on the entire signal path between SW0 and LED0. Partial credit will be given for honest effort.