1. Digital Logic
2. Tutorial: Creating Your First Project in Vivado

This tutorial is intended to guide you through the creation of your first Vivado project. It covers:

• How to create a new project;
• How to edit a project and add required source files;
• How to Synthesize and Implement a project, and how to generate a bitstream;
• And finally, how to program your Real Digital board.

You may want to refer back to this tutorial over the course of the first few projects as you gain confidence with the Vivado tool - you will need to repeat these same general steps whenever you create a new project in the future.

Step 1: Create a Vivado Project

Vivado Projects

Vivado “projects” are directory structures that contain all the files needed by a particular design. Some of these files are user-created source files that describe and constrain the design, but many others are system files created by Vivado to manage the design, simulation, and implementation of projects. In a typical design, you will only be concerned with the user-created source files. But, in the future, if you need more information about your design, or if you need more precise control over certain implementation details, you can access the other files as well.

When setting up a project in Vivado, you must give the project a unique name, choose a location to store all the project files, specify the type of project you are creating, add any pre-existing source files or constraints files (you might add existing sources if you are modifying an earlier design, but if you are creating a new design from scratch, you won’t add any existing files – you haven’t written them yet), and finally, select which physical chip you are designing for. These steps are illustrated below.

Start Vivado

Open Create Project Dialog

Set Project Name and Location

Select Project Type

Add Existing Sources

Add Constraints

Select Parts

How to find your Zynq 7000 SoC Parts

You can find the details about your xilinx part from the markings on the IC, in the reference manual for your board, on the page where you purchased the board, or in the board’s schematic.

From Identeifcation Marking on IC

Usually, you can find the part number directly from the marking on the surface of the logic device. In the picture below, you can see the part number for a Zynq-7000 device found on a Blackboard.

From Board Schematic

You can also find the part number from your board’s schematic. The figure below shows the Blackboard’s Zynq-7000 dvice identified in its schematic.

Check Project Configuration Summary

Vivado Project Window

Step 2: Edit The Project - Create source files

All projects require at least two types of source files – an HDL file (Verilog or VHDL) to describe the circuit, and a constraints file to provide the synthesizer with the information it needs to map your circuit into the target chip.

This tutorial presents the steps required to implement a Verilog circuit on your Real Digital board: first, a Verilog source file is created to define the circuits behavior (again, for this tutorial, you can simply copy or download the completed file rather than typing it); second, a constraints files is created to define how the Verilog circuit is mapped into the Xiling logic device (again, copied or downloaded for this tutorial); third, the Verilog source file and constraints file are synthesized into a “.bit” file that can be programmed onto your board; and fourth, the device is configured with the circuit.

After the Verilog source file is created, it can be directly simulated. Simulation (discussed in more detail later) lets you work with a computer model of a circuit, so you can check its behavior before taking the time to implement it in a physical device. The simulator lets you drive all the circuit inputs with varying patterns over time, and to check that the outputs behave as expected under all conditions.

After the constraint file is created, the design can be synthesized. The synthesis process translates Verilog source code into logical operations, and it uses the constraints file to map the logical operations into a given chip. In particular (for our needs here), the constraints file defines which Verilog circuit nodes are attached to which pins on the Xilinx chip package, and therefore, which circuit nodes are attached to which physical devices on your board. The synthesis process creates a “.bit” file that can be directly programmed into the Xilinx chip.

In this first tutorial, the Verilog and constraint source files are provided for you. Instead of creating them yourself as would normally be the case, you can simply copy them into empty source files, or download them and include them in your project directly. In later designs, you will create these files yourself.

`timescale 1ns / 1ps

    module project1_demo(
        input clk,
        output [15:0] led,
        output [7:0] seg,
        output [3:0] an
    );

    reg [23:0] counter = 24'd0;
    reg divclk = 1'b0;
    reg [3:0] round_counter = 4'd0;
    reg [15:0] led_reg;
    reg [7:0] seg_reg;

    /* Clock Divider: 100MHz -> 10Hz (100ms) */
    always @(posedge clk)
    begin
        if (counter == 24'd4999999) begin
            divclk <= ~divclk;
            counter <= 24'd0;
        end
        else begin
            divclk <= divclk;
            counter <= counter + 1'd1;
        end
    end

    always @(posedge divclk)
    begin
        round_counter <= round_counter + 1'd1;
    end

    always @(posedge divclk)
    begin
        if (round_counter == 4'd0) begin
            led_reg <= 16'hFFFE;
            seg_reg <= 8'hFE;
        end
        else begin
            seg_reg <= {seg_reg[6:0], seg_reg[7]};
            led_reg <= {led_reg[14:0], led_reg[15]};
        end
    end

    assign led = led_reg;
    assign an = 4'h0;
    assign seg = seg_reg;

    endmodule

Design Constraints

##Clock
#IO_L13P_T2_MRCC_35 Schematic name=SYSCLK
set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 4} [get_ports { clk }];

##LEDS
#IO_L14P_T2_SRCC_34 Schematic name=LD0
set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { led[0] }];
#IO_L14N_T2_SRCC_34 Schematic name=LD1
set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { led[1] }];
#IO_0_34 Schematic name=LD2
set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { led[2] }];
#IO_L15P_T2_DQS_34 Schematic name=LD3
set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { led[3] }];

##RGB_LEDS
#IO_L3P_T0_DWS_PUDC_B_34 Schematic name=LD4_R
set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { led[4] }];
#IO_25_34 Schematic name=LD4_G
set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { led[5] }];
#IO_L16N_T2_34 Schematic name=LD4_B
set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { led[6] }];

#IO_L17N_T2_34  Schematic name=LD5_R
set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { led[7] }];
#IO_L16P_T2_34 Schematic name=LD5_G
set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { led[8] }];
#IO_L22N_T3_34 Schematic name=LD5_B
set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { led[9] }];

#IO_L22P_T3_34  Schematic name=LD6_R
set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { led[10] }];
#IO_L18N_T2_34 Schematic name=LD6_G
set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { led[11] }];
#IO_L17P_T2_34 Schematic name=LD6_B
set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { led[12] }];

#IO_L8N_T1_34 Schematic name=LD7_R
set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { led[13] }];
#IO_L7P_T1_34 Schematic name=LD7_G
set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { led[14] }];
#IO_L7N_T1_34 Schematic name=LD7_B
set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { led[15] }];

##SevenSegmentDisplay
##anodes
#IO_L10P_T1_AD11P_35 Schematic name=SSEG_AN0
set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { an[0] }];
#IO_L13N_T2_MRCC_35 Schematic name=SSEG_AN1
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { an[1] }];
#IO_L8N_T1_AD10N_35 Schematic name=SSEG_AN2
set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { an[2] }];
#IO_L11P_T1_SRCC_35 Schematic name=SSEG_AN3
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { an[3] }];

##cathodes
#IO_L20P_T3_AD6P_35 Schematic name=SSEG_CA
set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { seg[0] }];
#IO_L19P_T3_35 Schematic name=SSEG_CB
set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { seg[1] }];
#IO_L14P_T2_AD4P_SRCC_35 Schematic name=SSEG_CC
set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { seg[2] }];
#IO_25_35 Schematic name=SSEG_CD
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { seg[3] }];
#IO_L8P_T1_AD10P_35 Schematic name=SSEG_CE
set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { seg[4] }];
#IO_L24N_T3_AD15N_35 Schematic name=SSEG_CF
set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { seg[5] }];
#IO_L8P_T1_AD10P_35 Schematic name=SSEG_CG
set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { seg[6] }];
#IO_L12N_T1_MRCC_35 Schematic name=SSEG_DP
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { seg[7] }];

Step 3: Synthesize, Implement, and Generate Bitstream

Implementation

Generate Bitstream

Step 4: Download Bitstream

Open Hardware Manager

Connecting Your Board via USB

Connecting your Board to Vivado

Verify that Your Board is Identified

Download Bitstream