Creating Your First Project in Vivado

Introduction to the Vivado Design Environment

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This tutorial is intended to guide you through the creation of your first Vivado project. It covers:

How to create a new project;
How to edit a project and add required source files;
How to Synthesize and Implement a project, and how to generate a bitstream;
And finally, how to program your Real Digital board.

You may want to refer back to this tutorial over the course of the first few projects as you gain confidence with the Vivado tool - you will need to repeat these same general steps whenever you create a new project in the future.

Step 1: Create a Vivado Project

Vivado Projects

Vivado “projects” are directory structures that contain all the files needed by a particular design. Some of these files are user-created source files that describe and constrain the design, but many others are system files created by Vivado to manage the design, simulation, and implementation of projects. In a typical design, you will only be concerned with the user-created source files. But, in the future, if you need more information about your design, or if you need more precise control over certain implementation details, you can access the other files as well.

When setting up a project in Vivado, you must give the project a unique name, choose a location to store all the project files, specify the type of project you are creating, add any pre-existing source files or constraints files (you might add existing sources if you are modifying an earlier design, but if you are creating a new design from scratch, you won’t add any existing files – you haven’t written them yet), and finally, select which physical chip you are designing for. These steps are illustrated below.

Start Vivado

In Windows, you can start Vivado by clicking the shortcut on the desktop or typing “Vivado” into the Windiws Start search box. In Linux, you can start Vivado using the command in a terminal window.

TUTORIAL: VIVADO TOOLS INSTALLATION.

After Vivado is started, the window should look similar to the picture in figure 1. Click on “New Project” in the Quick Start panel to open the New Project dialog box as shown below.

Figure 1. Vivado Start-Up Window

Open Create Project Dialog

Choose a name and location for the project. In the figure, the project name is “project_1”, which isn’t a particulary useful name. It’s usually a good idea to make the project name more descriptive, so you can more readily identify your designs in the future. For example, if you design a seven-segment controller, you might call the project “seven segment controller”. For projects related to coursework, you might include the course name and project number - for example, “ee214_project2”. You should avoid having spaces in the project name or location, because spaces can cause certain tools to fail.

You can choose any location to store the files and subdirectories that will be created for your new project. If the “Create project subdirectory” box is checked as shown in the figure, Vivado will automatically create a new subdirectory in your specificed directory for each new project (which is a good idea). In this example, I created a “VivadoProjects” directory on the C drive, but a better choice might be an on-line, backed-up directory (for example, using One drive or Google drive). Click Next to continue.

Figure 2. Create Project Dialog

Select Project Type

The “project type” selection configures the design tools to present the best interface for the type of project you are creating. Most often, and for all Real Digital courses, you will choose “RTL Project” to configure the tools for the creation of a new Verilog design (RTL stands for Register Transfer Language, which is a more general term describing hardware design languages like Verilog). If you are creating a new design from scratch, which is most tpyical in this course, you can check the “Do not specify sources at this time” to skip some unneeded steps. Click Next.

Figure 3. Select Project Type

Select Target AMD Device

AMD produces many different parts, and the CAD tools need to know what part you are using so they can produce the correct output files. The “Default Part” dialog box lists all relevant AMD part numbers, and you must select the exact part used from that list.

You can find the details about your AMD part from the markings printed on the chip, in the reference manual for your board, on the page where you purchased the board, or in the board’s schematic.

For example, the Blackboard uses a Zynq device with the following attributes:

Part Number	xc7z007sclg400-1
Family	Zynq-7000
Package	clg400
Speed Grade	-1
Temperature Grade	C

Figure 4. Select Zynq 7000 Part

Choose the xc7x007 part from the list as shown, and click Next to establish the project and open the main Vivado interface window.

Identification Marking on IC

You can typically find the AMD part number printed directly on the surface of the chip. In the picture below, you can see the part number for a Zynq-7000 device found on a Blackboard.

Identification Marking on Board Schematic

You can also find the part number from your board’s schematic. The figure below shows the Blackboard’s Zynq-7000 dvice identified in its schematic.

Add Existing Sources

Note: If you checked the “Do not specify sources at this time” in an earlier step, you will not see this box. In later projects, you can use this box to add existing Verilog source files.

In a typical new or early-stage design, you won’t add any existing sources because you haven’t created them yet. But as you complete more designs and build up a library of previously completed and known good designs, you may elect to add sources at this point and them use them in a new design.

You can also optionally use this interface to automate some steps in the creation of a new source file - we will use this interface in a later project.

Add Constraints

Note: If you checked the “Do not specify sources at this time” in an earlier step, you will not see this box. In later projects, you can use this box to add existing constraints files.

Constraint files provide information about the physical implementation of the design. They are created by the user and used by the synthesizer. Constraints are parameters that specify certain details about the design. As examples, some constraints identify which physical pins on the chip are to be connected to which named circuit nodes in your design; some constraints setup various physical attributes of the chip, like I/O pin drive strength (high or low current); and some constraints identify physical locations of certain circuit components.

The Design Constraints (.xdc filetpye) is the file format used for describing design constraints, and every design must have an .xdc file before it can be synthesized. Later in this tutorial, you will create a constraints file to identify which named circuit nodes must be connected to which physical pins. In later designs, you will probably just use the “master” .xdc file that is posted below.

Vivado Project Window

After the project has been defined as outined in the previous steps, the main Vivado window will be displayed. This is the main “working” interface where you enter and simulate your Verilog code, launch the synthesizer, and program your board. The left-most pane is the Flow Navigator that shows all the current files in the project, and all the processes that can operate on those files. To the right of the Flow Navigator is the Project Manager window where you enter source code, view simulation data, and interact with your design. The Console windows across the bottom show a running status, error messages, log files, and other outpur reports. Over the next few projects, you will interact with all of the panels.

Figure 7. Vivado Project Window

Step 2: Create source files

All projects require at least two types of source files – an HDL file (Verilog or VHDL) to describe the circuit, and a constraints file to provide the synthesizer with the information it needs to map your circuit into the target chip.

This tutorial presents the steps required to implement a Verilog circuit on your Real Digital board: first, a Verilog source file is created to define the circuits behavior (again, for this tutorial, you can simply copy or download the completed file rather than typing it); second, a constraints files is created to define how the Verilog circuit is mapped into the Xiling logic device (again, copied or downloaded for this tutorial); third, the Verilog source file and constraints file are synthesized into a “.bit” file that can be programmed onto your board; and fourth, the device is configured with the circuit.

After the Verilog source file is created, it can be directly simulated. Simulation (discussed in more detail later) lets you work with a computer model of a circuit, so you can check its behavior before taking the time to implement it in a physical device. The simulator lets you drive all the circuit inputs with varying patterns over time, and to check that the outputs behave as expected under all conditions.

After the constraint file is created, the design can be synthesized. The synthesis process translates Verilog source code into logical operations, and it uses the constraints file to map the logical operations into a given chip. In particular (for our needs here), the constraints file defines which Verilog circuit nodes are attached to which pins on the Xilinx chip package, and therefore, which circuit nodes are attached to which physical devices on your board. The synthesis process creates a “.bit” file that can be directly programmed into the Xilinx chip.

In this first tutorial, the Verilog and constraint source files are provided for you. Instead of creating them yourself as would normally be the case, you can simply copy them into empty source files, or download them and include them in your project directly. In later designs, you will create these files yourself.

There are many ways to define a logic circuit, and many types of source files including VHDL, Verilog, EDIF and NGC netlists, DCP checkpoint files, TCL scripts, System C files, and many others. We will use the Verilog language in this course, and introduce it gradually over the first several projects. For now, you can get familiar with some of the basic concepts in the posted Verilog Introductory document.

A breif introduction to Verilog

Design Sources

To create a Verilog source file for your project, click on “Add Sources” in the Flow Navigator panel to bring up the Add Sources dialog box.

Figure 8. Add or create design sources using Add Source Dialog

Check “Add or create design sources” to define a new Verilog source file and click Next.

Figure 9. Create Design Source File

In this dialog box, you can add existing source files or directories, or create new files. In this exercise, we will create a new source file, so click “Create file” to bring up the “Create Source File” panel.

Figure 10. Create Design Source File

Select Verilog as the file type, and select a name for your source file. A descriptive name that identifies something about the source file is recommended.

Figure 11. Name Design Source File

The next window is a “Wizard” that you can use to define input and output signals to your Verilog source file. All Verilog source files must define their input and output signals, and you can either type them into this window, or just type the same information directly into the source file. For now, you will cut-and-paste an entire Verilog file that includes input and output definitions, so you can pass through the next two windows by clicking “OK” and “Yes” without entering any information.

Figure 12. Input and Output definition “wizard”

You will now see your newly-created empty source file listed underneath Design Sources folder in the Sources panel. Double click the file name to open the file, and replace the contents (copy and paste) with the code below.

Alternative: Download and Add Source

Instead of creating a source file by using copy and paste as described above, you can alternatively download the project1_demo.v file and add it to your project using the Add Sources button in Add Sources dialog.

Figure 13. project1_demo appears in design sources

`timescale 1ns / 1ps

    module project1_demo(
        input clk,
        output [15:0] led,
        output [7:0] seg,
        output [3:0] an
    );

    reg [23:0] counter = 24'd0;
    reg divclk = 1'b0;
    reg [3:0] round_counter = 4'd0;
    reg [15:0] led_reg;
    reg [7:0] seg_reg;

    /* Clock Divider: 100MHz -> 10Hz (100ms) */
    always @(posedge clk)
    begin
        if (counter == 24'd4999999) begin
            divclk <= ~divclk;
            counter <= 24'd0;
        end
        else begin
            divclk <= divclk;
            counter <= counter + 1'd1;
        end
    end

    always @(posedge divclk)
    begin
        round_counter <= round_counter + 1'd1;
    end

    always @(posedge divclk)
    begin
        if (round_counter == 4'd0) begin
            led_reg <= 16'hFFFE;
            seg_reg <= 8'hFE;
        end
        else begin
            seg_reg <= {seg_reg[6:0], seg_reg[7]};
            led_reg <= {led_reg[14:0], led_reg[15]};
        end
    end

    assign led = led_reg;
    assign an = 4'h0;
    assign seg = seg_reg;

    endmodule

After adding the code, your window should look like the image on the right. Now the constraints file can be added, and then we can synthesize the design and download it to the board.

Figure 14. Create Design Source File

Design Constraints

Verilog source files only describe circuit behavior. You must also provide a constraints file to map your design into the physical chip and board you are working with.

To create a constraints file, highlight the Constraints heading in the Sources panel, and the click on “Add Sources” in the Flow Navigtor.

Figure 15. Add Source to Design Constraints

In the Add Sources dialog box that appears, select “Add or create constraints” and hit Next.

Figure 16. Add or create design constraints using Add Source Dialog

Select “Create File” to define a new constraints file. Note that constraints files use the “xdc” suffix, and are often referred to as “XDC” files.

In the next two boxes, choose a file name for the XDC file - it is OK to use the same name as you used for the Verilog source file (in fact, using the same root name can help identify where the .xdc file is used later on). Click OK, and Finish to add the constraints file to your project.

You will now see the “Requirements1.xdc” file listed under the Constraints heading in the Flow Navigator. Double click on the name to open the file, and cut-and-paste the code below into the file.

Figure 8. Double Click to Edit project1.xdc

##Clock
#IO_L13P_T2_MRCC_35 Schematic name=SYSCLK
set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }];
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 4} [get_ports { clk }];

##LEDS
#IO_L14P_T2_SRCC_34 Schematic name=LD0
set_property -dict { PACKAGE_PIN N20   IOSTANDARD LVCMOS33 } [get_ports { led[0] }];
#IO_L14N_T2_SRCC_34 Schematic name=LD1
set_property -dict { PACKAGE_PIN P20   IOSTANDARD LVCMOS33 } [get_ports { led[1] }];
#IO_0_34 Schematic name=LD2
set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { led[2] }];
#IO_L15P_T2_DQS_34 Schematic name=LD3
set_property -dict { PACKAGE_PIN T20   IOSTANDARD LVCMOS33 } [get_ports { led[3] }];

##RGB_LEDS
#IO_L3P_T0_DWS_PUDC_B_34 Schematic name=LD4_R
set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { led[4] }];
#IO_25_34 Schematic name=LD4_G
set_property -dict { PACKAGE_PIN T19   IOSTANDARD LVCMOS33 } [get_ports { led[5] }];
#IO_L16N_T2_34 Schematic name=LD4_B
set_property -dict { PACKAGE_PIN W20   IOSTANDARD LVCMOS33 } [get_ports { led[6] }];

#IO_L17N_T2_34  Schematic name=LD5_R
set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { led[7] }];
#IO_L16P_T2_34 Schematic name=LD5_G
set_property -dict { PACKAGE_PIN V20   IOSTANDARD LVCMOS33 } [get_ports { led[8] }];
#IO_L22N_T3_34 Schematic name=LD5_B
set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { led[9] }];

#IO_L22P_T3_34  Schematic name=LD6_R
set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { led[10] }];
#IO_L18N_T2_34 Schematic name=LD6_G
set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { led[11] }];
#IO_L17P_T2_34 Schematic name=LD6_B
set_property -dict { PACKAGE_PIN Y18   IOSTANDARD LVCMOS33 } [get_ports { led[12] }];

#IO_L8N_T1_34 Schematic name=LD7_R
set_property -dict { PACKAGE_PIN Y14   IOSTANDARD LVCMOS33 } [get_ports { led[13] }];
#IO_L7P_T1_34 Schematic name=LD7_G
set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { led[14] }];
#IO_L7N_T1_34 Schematic name=LD7_B
set_property -dict { PACKAGE_PIN Y17   IOSTANDARD LVCMOS33 } [get_ports { led[15] }];

##SevenSegmentDisplay
##anodes
#IO_L10P_T1_AD11P_35 Schematic name=SSEG_AN0
set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { an[0] }];
#IO_L13N_T2_MRCC_35 Schematic name=SSEG_AN1
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { an[1] }];
#IO_L8N_T1_AD10N_35 Schematic name=SSEG_AN2
set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { an[2] }];
#IO_L11P_T1_SRCC_35 Schematic name=SSEG_AN3
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { an[3] }];

##cathodes
#IO_L20P_T3_AD6P_35 Schematic name=SSEG_CA
set_property -dict { PACKAGE_PIN K14   IOSTANDARD LVCMOS33 } [get_ports { seg[0] }];
#IO_L19P_T3_35 Schematic name=SSEG_CB
set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { seg[1] }];
#IO_L14P_T2_AD4P_SRCC_35 Schematic name=SSEG_CC
set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { seg[2] }];
#IO_25_35 Schematic name=SSEG_CD
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { seg[3] }];
#IO_L8P_T1_AD10P_35 Schematic name=SSEG_CE
set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { seg[4] }];
#IO_L24N_T3_AD15N_35 Schematic name=SSEG_CF
set_property -dict { PACKAGE_PIN J16   IOSTANDARD LVCMOS33 } [get_ports { seg[5] }];
#IO_L8P_T1_AD10P_35 Schematic name=SSEG_CG
set_property -dict { PACKAGE_PIN H18   IOSTANDARD LVCMOS33 } [get_ports { seg[6] }];
#IO_L12N_T1_MRCC_35 Schematic name=SSEG_DP
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { seg[7] }];

The main Vivado window now shows three file tabs that you can click on to view the source files associated with the project.

Figure 17. Double Click to Edit project1.xdc

Step 3: Synthesize, Implement, and Generate Bitstream

Synthesis

After your Verilog and constraint files are complete, you can Synthesize the design project. In the synthesis process, Verilog code is translated into a “netlist” that defines all the required circuit components needed by the design (these components are the programmable parts of the targeted logic device - more on that later). You can start the Synthesize process by clicking on Run Synthesis in the Flow Navigator panel as shown. Note that a “Launch Runs” dialog box opens - you can accept the defaults by clicking “OK”, and you can also check the “Don’t show this dialog again” to keep it from popping up in the future.

When synthesis is running, you can select the “Tcl Console” panel located at the bottom of the main Vivado window to see a log of the currently running processes. Any errors that occur during the synthesis process will be described in the log. Also note the the main Vivado window shows a rotating symbol in the upper right corner whenever an active process (like synthesis) is running.

Figure 18. Start Synthesis process and monitor the systhesis log

Implementation

After the design is synthesized, you must run the Implementation process. The implementation process maps the synthesized design onto the Xilinx chip targeted by the design. You can either select “Run Implementation” and click OK in the Synthesis Complete dialog box that opens when synthesis is complete, or you can click on the “Run Implementation” process in the Flow Navigator.

When the implementation process is running, the Tcl Console panel at the bottom of main Vivado window will show details about any errors that occur.

Generate Bitstream

After the design is successfully implemented, you can create a .bit file by selecting “Generate Bitstream” and clicking OK in the dialog box that opens when Implmentation is complete, or by clicking on the Generate Bitstream process located in the Flow Navigator panel under the Program and Debug heading. This process translates the implemented design into a bitstream which can be directly programmed into your board’s device.

Step 4: Download Bitstream

Open Hardware Manager

After the bitstream is successfully generated, you can program your board using the Hardware Manager tool avaialble in the Flow Navigator. You can open the hardware manager by selecting “Open Hardware Manager” and clicking OK in the dialog box that opens when Generate Bitsteram process is complete, or by clicking on the Open Hardware Manager process located in the Flow Navigator panel under the Program and Debug heading.

Figure 19. Open Hardware Manager

Connecting Your Board via USB

Connect your Blackboard to your Computer with a micro-USB cable. Make sure you connect the micro-USB cable to the port labeled “PROG UART”. Turn on your board by moving the switch in the top-left corner to the on position. You’ll see a red LED light up by the switch when it powers on. If your board doesn’t power on, check that the blue jumper by the port labeled “EXTP” is set to “USB”. The figure shows a powered on Blackboard, with the correct jumper setting.

Connecting your Board to Vivado

The Harware Manager tool connects the Vivado tool to an AMD device on a target hardware platform like the Blackboard. For Vivado to find a target board, the board must be turned on and connected via USB. When the Hardware Manager first opens, it presents an “Open Target” process that actively scans all USB connections, looking for a connection to a known AMD hardware platform. After the target hardware is identified and connected, you can use the Hardware Manager to download a programming file to board.

Click on “Open target” at the top of the Hardware Manager window as shown (or you can also click on the Open Target process under the Program and Debug heading in the Flow Navigator).

Figure 20. Auto Connect Target

After a brief delay, the Hardware Manager will locate the Blackboard, display the detected hardware parameters (shown in the Green box), and display a “Program Device” process (Red box). Click on “Program Device” to bring up the Program Device Dialog box.

Figure 21. Auto Connect Target

If you’re having trouble connecting in Linux you may need to install cable drivers. Follow the tutorial: TUTORIAL: Installing Linux Cable Drivers

Download Bitstream

The Program Device Dialog Box will default to pointing at the most recently created .bit file that was produced earier in this project. Click Program, and your design will be transferred to the hardware platform.

Figure 22. Program Device