HDMI

Using Real Digital's HDMI IP Core

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Introduction

You can use the HDMI port as output if your monitor has HDMI or DVI port. HDMI stands for High-Definition Media Interface. It transfer uncompressed video data with compressed and uncompressed audio data as well. Unlike VGA where RGB are encoded as analog voltage, HDMI is a digital interface using TMDS (Transition Minimized Differential Signaling) technology that encodes uncompressed digital video data and audio data from display controller to the display monitor. Due to the nature of signal encoding, the toggling speed of the signal is usually higher than 10 times the pixel clock frequency (i.e. for 720p, if the pixel clock is 74.25MHz, the speed of HDMI signal is higher than 742.5MHz). So, on Blackboard, even though VGA port can handle 1080P, the HDMI port on Blackboard can only handle the video resolution up to 720P due to the switching speed limit of FPGA pins.

Figure 1. HDMI IP Core
Figure 1. HDMI IP Core

Here is HDMI/DVI IP Core that you can use in your design that transfers the VGA signals into HDMI signals. Unzip the file. To add the IP to your block design right click on an empty space within the block design. Select IP Settings and under IP tab choose Repository; add the hdmi_tx_1.0 folder, click apply and OK. Then you can add the HDMI/DVI IP to your block design. The HDMI core is shown in Figure 1, and the port definition is shown in the table below.

Signal Name Description Comments
pxl_clk Pixel Clock Input (Buffered) For 720P, it should be around 74.25MHz
pxl_clkx5 5x Pixel Clock Input (buffered) For 720P, it will be 5 x 74.25Mhz = 371.25MHz. Used to drive HDMI Encoding Logic.
pxl_clk_locked Pixel Clock Locked Signal Active High signal indicates PXLCLK_I and PXLCLK_5X_I are stable. Should be handled by the MMCM that generates pixel clocks.
rst Active High Reset Active High should be asserted, at least, until pixel clocks are stable. Should be handled by reset controller of the whole system.
red; green; blue Red, Green and Blue channel (default to 8-bit each channel)
hsync Horizontal Synchronization Low during the synchronization pulse, and High otherwise.
vsynq Vertical Synchronization Low during the synchronization pulse, and High otherwise.
vde Data Enable Signal High when in the active display area (excluding front porch and back porch), and Low otherwise.
HDMI_CLK_P; HDMI_CLK_N; HDMI_D0_P; HDMI_D0_N; HDMI_D1_P; HDMI_D1_N; HDMI_D2_P; HDMI_D2_N HDMI Interface Signals